JPS5542003A - Wave-form delay sampling circuit - Google Patents

Wave-form delay sampling circuit

Info

Publication number
JPS5542003A
JPS5542003A JP11450378A JP11450378A JPS5542003A JP S5542003 A JPS5542003 A JP S5542003A JP 11450378 A JP11450378 A JP 11450378A JP 11450378 A JP11450378 A JP 11450378A JP S5542003 A JPS5542003 A JP S5542003A
Authority
JP
Japan
Prior art keywords
counter
gate
hold circuit
down counter
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11450378A
Other languages
Japanese (ja)
Inventor
Masatoshi Kitagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11450378A priority Critical patent/JPS5542003A/en
Publication of JPS5542003A publication Critical patent/JPS5542003A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To provide simplified constitution with higher accuracy by adapting digital system circuit.
CONSTITUTION: Sample signals generated by chopping observed wave-form by means of chopper 1 which is driven in a constant period are distributed to hold circuit 4, refrence pulse generator 5, refrence pulse counter 6, and up-and-down counter 9. The hold circuit 4 inputs and holds sample signal via gate 3 of which opening is controlled by gate signal, and the up-and-down counter 9 memorizes information from counter 6 in response to load signals which are produced synchronously with chopper 1. A predetermined number of pulses generated by pulse generator 5 are reduced until information memorized in up-and-down counter 9 reaches to zero, and signal generated when said information becomes zero constitutes said gate signal of the gate 3 on the input side of the hold circuit 4.
COPYRIGHT: (C)1980,JPO&Japio
JP11450378A 1978-09-20 1978-09-20 Wave-form delay sampling circuit Pending JPS5542003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11450378A JPS5542003A (en) 1978-09-20 1978-09-20 Wave-form delay sampling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11450378A JPS5542003A (en) 1978-09-20 1978-09-20 Wave-form delay sampling circuit

Publications (1)

Publication Number Publication Date
JPS5542003A true JPS5542003A (en) 1980-03-25

Family

ID=14639375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11450378A Pending JPS5542003A (en) 1978-09-20 1978-09-20 Wave-form delay sampling circuit

Country Status (1)

Country Link
JP (1) JPS5542003A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60137716U (en) * 1984-02-21 1985-09-12 小川コンベヤ株式会社 Conveyor chain structure
JPS61172431A (en) * 1985-01-28 1986-08-04 Fujisoku:Kk Sampling signal generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60137716U (en) * 1984-02-21 1985-09-12 小川コンベヤ株式会社 Conveyor chain structure
JPS61172431A (en) * 1985-01-28 1986-08-04 Fujisoku:Kk Sampling signal generating circuit

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