JPS5659304A - Interface device for sequence control - Google Patents

Interface device for sequence control

Info

Publication number
JPS5659304A
JPS5659304A JP13551379A JP13551379A JPS5659304A JP S5659304 A JPS5659304 A JP S5659304A JP 13551379 A JP13551379 A JP 13551379A JP 13551379 A JP13551379 A JP 13551379A JP S5659304 A JPS5659304 A JP S5659304A
Authority
JP
Japan
Prior art keywords
input
signal
output
bus line
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13551379A
Other languages
Japanese (ja)
Inventor
Masaaki Murakoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shibaura Machine Co Ltd
Original Assignee
Toshiba Machine Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Machine Co Ltd filed Critical Toshiba Machine Co Ltd
Priority to JP13551379A priority Critical patent/JPS5659304A/en
Publication of JPS5659304A publication Critical patent/JPS5659304A/en
Pending legal-status Critical Current

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  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To control a number of device to be controlled, by a simple operation and a little labor, by deciding the input/output from a signal on the bus line, and detecting its timing.
CONSTITUTION: A signal on the bus line BL is input to both the counter 102 and the input data detection circuit 105, after its waveform and level have been converted. The counter 102 counts the input pulses and inputs its output signal to the comparator 103. On the other hand, the address setting device 104 inputs its own address signal in advance to the comparator 103, and the comparator 103 generates a coincidence signal COIN when the counter 102 takes the same value as its own address. The input/output gate is operated in accordance with this coincidence signal COIN. On the other hand, the input/output data detection circuit 105 decides whether the data on the bus line is an input element or an output element, and connects the device to be controlled and the bus line BL.
COPYRIGHT: (C)1981,JPO&Japio
JP13551379A 1979-10-19 1979-10-19 Interface device for sequence control Pending JPS5659304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13551379A JPS5659304A (en) 1979-10-19 1979-10-19 Interface device for sequence control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13551379A JPS5659304A (en) 1979-10-19 1979-10-19 Interface device for sequence control

Publications (1)

Publication Number Publication Date
JPS5659304A true JPS5659304A (en) 1981-05-22

Family

ID=15153513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13551379A Pending JPS5659304A (en) 1979-10-19 1979-10-19 Interface device for sequence control

Country Status (1)

Country Link
JP (1) JPS5659304A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5442581A (en) * 1977-09-09 1979-04-04 Mitsubishi Electric Corp Control signal terating unit of electromagnetic contactor
JPS5476786A (en) * 1977-11-30 1979-06-19 Hitachi Ltd Input and output unit of sequence controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5442581A (en) * 1977-09-09 1979-04-04 Mitsubishi Electric Corp Control signal terating unit of electromagnetic contactor
JPS5476786A (en) * 1977-11-30 1979-06-19 Hitachi Ltd Input and output unit of sequence controller

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