FR2376459A1 - ARITHMETIC AND LOGICAL UNIT - Google Patents

ARITHMETIC AND LOGICAL UNIT

Info

Publication number
FR2376459A1
FR2376459A1 FR7800099A FR7800099A FR2376459A1 FR 2376459 A1 FR2376459 A1 FR 2376459A1 FR 7800099 A FR7800099 A FR 7800099A FR 7800099 A FR7800099 A FR 7800099A FR 2376459 A1 FR2376459 A1 FR 2376459A1
Authority
FR
France
Prior art keywords
arithmetic
signal
carry input
receives
logical unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7800099A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/756,457 external-priority patent/US4084253A/en
Priority claimed from US05/756,458 external-priority patent/US4081860A/en
Priority claimed from US05/756,456 external-priority patent/US4084252A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2376459A1 publication Critical patent/FR2376459A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne une unité arithmétique et logique fonctionnant en mode de courant. Elle comporte une première partie qui reçoit deux multiplets d'entrée, un signal d'entrée de retenue, un signal de commande de mode, et produisant un signal de sortie binaire résultant en fonction du signal de commande de mode, et une seconde partie qui reçoit un signal d'entrée de retenue et un signal de dédoublement d'entrée de retenue, et produisant des signaux de parité et d'erreur en plus des résultats de l'opération arithmétique ou logique. Application aux calculateurs numériques.Disclosed is an arithmetic and logic unit operating in current mode. It has a first part which receives two input bytes, a carry input signal, a mode control signal, and produces a resulting binary output signal according to the mode control signal, and a second part which receives a carry input signal and a carry input doubling signal, and produces parity and error signals in addition to the results of the arithmetic or logic operation. Application to digital computers.

FR7800099A 1977-01-03 1978-01-03 ARITHMETIC AND LOGICAL UNIT Pending FR2376459A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/756,457 US4084253A (en) 1977-01-03 1977-01-03 Current mode arithmetic logic circuit with parity prediction and checking
US05/756,458 US4081860A (en) 1977-01-03 1977-01-03 Current mode 4-bit arithmetic logic unit with parity
US05/756,456 US4084252A (en) 1977-01-03 1977-01-03 Current mode 5-bit arithmetic logic unit with parity

Publications (1)

Publication Number Publication Date
FR2376459A1 true FR2376459A1 (en) 1978-07-28

Family

ID=27419490

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7800099A Pending FR2376459A1 (en) 1977-01-03 1978-01-03 ARITHMETIC AND LOGICAL UNIT

Country Status (2)

Country Link
FR (1) FR2376459A1 (en)
GB (1) GB1595479A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1525624A (en) * 1966-06-04 1968-05-17 Zuse Kg Method of determining errors in arithmetic units
US3649817A (en) * 1969-07-31 1972-03-14 Ibm Arithmetic and logical unit with error checking
US3699323A (en) * 1970-12-23 1972-10-17 Ibm Error detecting and correcting system and method
US3758760A (en) * 1972-04-07 1973-09-11 Honeywell Inf Systems Error detection for arithmetic and logical unit modules
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1525624A (en) * 1966-06-04 1968-05-17 Zuse Kg Method of determining errors in arithmetic units
US3649817A (en) * 1969-07-31 1972-03-14 Ibm Arithmetic and logical unit with error checking
US3699323A (en) * 1970-12-23 1972-10-17 Ibm Error detecting and correcting system and method
US3758760A (en) * 1972-04-07 1973-09-11 Honeywell Inf Systems Error detection for arithmetic and logical unit modules
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/74 *

Also Published As

Publication number Publication date
GB1595479A (en) 1981-08-12

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