FR2374690A1 - Dispositif de controle de parite pour detecter les defaillances de lignes de mots dans une memoire d'un systeme de traitement de donnees - Google Patents

Dispositif de controle de parite pour detecter les defaillances de lignes de mots dans une memoire d'un systeme de traitement de donnees

Info

Publication number
FR2374690A1
FR2374690A1 FR7733081A FR7733081A FR2374690A1 FR 2374690 A1 FR2374690 A1 FR 2374690A1 FR 7733081 A FR7733081 A FR 7733081A FR 7733081 A FR7733081 A FR 7733081A FR 2374690 A1 FR2374690 A1 FR 2374690A1
Authority
FR
France
Prior art keywords
memory
control device
data processing
failures
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7733081A
Other languages
English (en)
Other versions
FR2374690B1 (fr
Inventor
Frederick J Aichelmann Jr
Nino M Dipilato
Thomas P Fehn
George J Rudy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2374690A1 publication Critical patent/FR2374690A1/fr
Application granted granted Critical
Publication of FR2374690B1 publication Critical patent/FR2374690B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Dispositif de contrôle associé à une mémoire dans laquelle une ligne de mot à n multiplets, lorsqu'elle est défaillante, ne comporte que des << 0 >> ou des << 1 >>. Un circuit inverseur 3 inverse le bit de parité d'un multiplet d'une ligne de mot au moment de l'écriture et de la lecture en mémoire. Un circuit de comparaison dans 16 compare le bit de parité inversé transmis par 20 au bit recalculé à partir des bits de données transmis par 15. (n-1) autres circuits de comparaison dans 21... 22 comparent les bits de parité transmis par 23... 24 aux bits de parité recalculés à partir des bits de données transmis par 21... 29 pour les (n-1) autres multiplets. Application aux mémoires des sytèmes de traitement de donnees pour en augmenter la fiabilité.
FR7733081A 1976-12-20 1977-10-24 Dispositif de controle de parite pour detecter les defaillances de lignes de mots dans une memoire d'un systeme de traitement de donnees Granted FR2374690A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/752,336 US4103823A (en) 1976-12-20 1976-12-20 Parity checking scheme for detecting word line failure in multiple byte arrays

Publications (2)

Publication Number Publication Date
FR2374690A1 true FR2374690A1 (fr) 1978-07-13
FR2374690B1 FR2374690B1 (fr) 1980-08-08

Family

ID=25025875

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7733081A Granted FR2374690A1 (fr) 1976-12-20 1977-10-24 Dispositif de controle de parite pour detecter les defaillances de lignes de mots dans une memoire d'un systeme de traitement de donnees

Country Status (5)

Country Link
US (1) US4103823A (fr)
JP (1) JPS5376713A (fr)
DE (1) DE2752377A1 (fr)
FR (1) FR2374690A1 (fr)
GB (1) GB1534129A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2435088A1 (fr) * 1978-08-30 1980-03-28 Int Standard Electric Corp Agencement de circuit pour le traitement de subdivisions de mots dans des systemes d'ordinateur
FR2479534A1 (fr) * 1980-03-31 1981-10-02 Western Electric Co Circuit de detection d'erreur pour une memoire

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234955A (en) * 1979-01-26 1980-11-18 International Business Machines Corporation Parity for computer system having an array of external registers
JPS5853097A (ja) * 1981-09-24 1983-03-29 Fujitsu Ltd キ−記憶のエラ−処理方式
US4453251A (en) * 1981-10-13 1984-06-05 Burroughs Corporation Error-correcting memory with low storage overhead and fast correction mechanism
US4617664A (en) * 1984-06-29 1986-10-14 International Business Machines Corporation Error correction for multiple bit output chips
US4809276A (en) * 1987-02-27 1989-02-28 Hutton/Prc Technology Partners 1 Memory failure detection apparatus
JPS63257854A (ja) * 1987-04-15 1988-10-25 Nec Corp Ｌｒｕメモリ障害検出回路
ATE125404T1 (de) * 1989-01-27 1995-08-15 Siemens Ag Verfahren zur behandlung von paritätsüberwachbaren binärcodeworten, die im zuge ihrer übertragung eine digitale dämpfung und/oder codekonvertierung erfahren.
US5644583A (en) * 1992-09-22 1997-07-01 International Business Machines Corporation Soft error correction technique and system for odd weight row error correction codes
DK0643350T3 (da) * 1993-08-10 1998-09-28 Siemens Ag Fremgangsmåde til identificering af adresseringsfejl i lagre for digitale, binært kodede dataord
US6519735B1 (en) * 1998-12-22 2003-02-11 Intel Corporation Method and apparatus for detecting errors in data output from memory and a device failure in the memory
DE102005016051B4 (de) * 2005-04-07 2019-06-13 Infineon Technologies Ag Speicherüberprüfungsvorrichtung und Verfahren zum Überprüfen eines Speichers
DE102005016050A1 (de) * 2005-04-07 2006-10-12 Infineon Technologies Ag Speicherfehlererkennungsvorrichtung und Verfahren zum Erkennen eines Speicherfehlers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
NL7415966A (nl) * 1974-12-09 1976-06-11 Philips Nv Werkwijze en inrichting voor het opslaan van binaire informatie-elementen.
US4016409A (en) * 1976-03-01 1977-04-05 Burroughs Corporation Longitudinal parity generator for use with a memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2435088A1 (fr) * 1978-08-30 1980-03-28 Int Standard Electric Corp Agencement de circuit pour le traitement de subdivisions de mots dans des systemes d'ordinateur
FR2479534A1 (fr) * 1980-03-31 1981-10-02 Western Electric Co Circuit de detection d'erreur pour une memoire

Also Published As

Publication number Publication date
DE2752377A1 (de) 1978-06-29
US4103823A (en) 1978-08-01
JPS5376713A (en) 1978-07-07
JPS578560B2 (fr) 1982-02-17
GB1534129A (en) 1978-11-29
FR2374690B1 (fr) 1980-08-08

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Legal Events

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ST Notification of lapse