FR2373126A1 - Dispositifs de memoire a charges couplees avec emmagasinage de niveaux de charge multiples et procede d'utilisation de tels dispositifs - Google Patents

Dispositifs de memoire a charges couplees avec emmagasinage de niveaux de charge multiples et procede d'utilisation de tels dispositifs

Info

Publication number
FR2373126A1
FR2373126A1 FR7731856A FR7731856A FR2373126A1 FR 2373126 A1 FR2373126 A1 FR 2373126A1 FR 7731856 A FR7731856 A FR 7731856A FR 7731856 A FR7731856 A FR 7731856A FR 2373126 A1 FR2373126 A1 FR 2373126A1
Authority
FR
France
Prior art keywords
charge
devices
cell
storage
memory devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7731856A
Other languages
English (en)
French (fr)
Other versions
FR2373126B1 (enExample
Inventor
Narasipur G Anantha
Fung Y Chang
Barry J Rubin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2373126A1 publication Critical patent/FR2373126A1/fr
Application granted granted Critical
Publication of FR2373126B1 publication Critical patent/FR2373126B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/34—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C19/36—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using multistable semiconductor elements

Landscapes

  • Shift Register Type Memory (AREA)
  • Networks Using Active Elements (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
FR7731856A 1976-12-06 1977-10-14 Dispositifs de memoire a charges couplees avec emmagasinage de niveaux de charge multiples et procede d'utilisation de tels dispositifs Granted FR2373126A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/747,658 US4139910A (en) 1976-12-06 1976-12-06 Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature

Publications (2)

Publication Number Publication Date
FR2373126A1 true FR2373126A1 (fr) 1978-06-30
FR2373126B1 FR2373126B1 (enExample) 1980-08-08

Family

ID=25006081

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7731856A Granted FR2373126A1 (fr) 1976-12-06 1977-10-14 Dispositifs de memoire a charges couplees avec emmagasinage de niveaux de charge multiples et procede d'utilisation de tels dispositifs

Country Status (8)

Country Link
US (1) US4139910A (enExample)
JP (1) JPS5370736A (enExample)
DE (1) DE2753570A1 (enExample)
FR (1) FR2373126A1 (enExample)
GB (1) GB1544746A (enExample)
IT (1) IT1113785B (enExample)
NL (1) NL7712883A (enExample)
SE (1) SE7713735L (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4206370A (en) * 1976-12-20 1980-06-03 Motorola, Inc. Serial-parallel-loop CCD register
US4196389A (en) * 1978-07-13 1980-04-01 International Business Machines Corporation Test site for a charged coupled device (CCD) array
US4246496A (en) * 1978-07-17 1981-01-20 International Business Machines Corporation Voltage-to-charge transducer
US4185324A (en) * 1978-08-03 1980-01-22 Ncr Corporation Data storage system
US4202046A (en) * 1978-09-01 1980-05-06 Ncr Corporation Data storage system for storing multilevel signals
US4300210A (en) * 1979-12-27 1981-11-10 International Business Machines Corp. Calibrated sensing system
US4306300A (en) * 1979-12-31 1981-12-15 International Business Machines Corporation Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits
US4459609A (en) * 1981-09-14 1984-07-10 International Business Machines Corporation Charge-stabilized memory
US4916657A (en) * 1985-12-12 1990-04-10 Alcatel Usa, Corp. Single instruction multiple data (SIMD) cellular array processing apparatus employing multiple state logic for coupling to data buses
US5218569A (en) 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6353554B1 (en) * 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
AUPO799197A0 (en) * 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Image processing method and apparatus (ART01)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3772658A (en) * 1971-02-05 1973-11-13 Us Army Electronic memory having a page swapping capability
US3789247A (en) * 1972-07-03 1974-01-29 Ibm Dynamically ordered bidirectional shift register having charge coupled devices
US3930255A (en) * 1974-02-06 1975-12-30 Us Navy Analog to digital conversion by charge transfer device
US3891977A (en) * 1974-07-15 1975-06-24 Fairchild Camera Instr Co Charge coupled memory device
US3958210A (en) * 1975-02-05 1976-05-18 Rca Corporation Charge coupled device systems

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EXBK/75 *
EXBK/76 *
NV8093/76 *

Also Published As

Publication number Publication date
NL7712883A (nl) 1978-06-08
FR2373126B1 (enExample) 1980-08-08
SE7713735L (sv) 1978-06-07
IT1113785B (it) 1986-01-20
JPS5610720B2 (enExample) 1981-03-10
US4139910A (en) 1979-02-13
JPS5370736A (en) 1978-06-23
DE2753570A1 (de) 1978-06-08
GB1544746A (en) 1979-04-25

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Legal Events

Date Code Title Description
ST Notification of lapse