FR2357004A1 - Dispositif d'echantillonnage et de recuperation de donnees par la methode d'enregistrement a double transition comportant des moyens de retard - Google Patents

Dispositif d'echantillonnage et de recuperation de donnees par la methode d'enregistrement a double transition comportant des moyens de retard

Info

Publication number
FR2357004A1
FR2357004A1 FR7719627A FR7719627A FR2357004A1 FR 2357004 A1 FR2357004 A1 FR 2357004A1 FR 7719627 A FR7719627 A FR 7719627A FR 7719627 A FR7719627 A FR 7719627A FR 2357004 A1 FR2357004 A1 FR 2357004A1
Authority
FR
France
Prior art keywords
delay means
sampling
bits
method including
recording method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7719627A
Other languages
English (en)
Other versions
FR2357004B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2357004A1 publication Critical patent/FR2357004A1/fr
Application granted granted Critical
Publication of FR2357004B1 publication Critical patent/FR2357004B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un dispositif d'échantillonnage et de récupération de données On utilise pour échantillonner des bits de données et d'horloge des moyens de double retard tels que des registres à décalage agencés pour que les premiers de ces moyens, couplés pour recevoir des bits, ne contiennent à chaque instant pas plus d'un seul bit La réception d'un bit se trouvant approximativement au point médian des seconds moyens de retard qui sont couplés pour recevoir les bits des premiers moyens de retard provoque la génération d'un signal d'échantillonnage en réponse auquel une détermination sert à savoir si un autre bit a eté reçu par les premiers moyens de retard. Une logique complémentaire sert à récupérer les bits de données. Application au traitement des données.
FR7719627A 1976-06-28 1977-06-27 Dispositif d'echantillonnage et de recuperation de donnees par la methode d'enregistrement a double transition comportant des moyens de retard Granted FR2357004A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/700,276 US4034348A (en) 1976-06-28 1976-06-28 Apparatus, including delay means, for sampling and recovering data recorded by the double transition recording technique

Publications (2)

Publication Number Publication Date
FR2357004A1 true FR2357004A1 (fr) 1978-01-27
FR2357004B1 FR2357004B1 (fr) 1985-03-15

Family

ID=24812888

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7719627A Granted FR2357004A1 (fr) 1976-06-28 1977-06-27 Dispositif d'echantillonnage et de recuperation de donnees par la methode d'enregistrement a double transition comportant des moyens de retard

Country Status (9)

Country Link
US (1) US4034348A (fr)
JP (1) JPS533210A (fr)
AU (1) AU506388B2 (fr)
BE (1) BE856032A (fr)
CA (1) CA1073115A (fr)
DE (1) DE2728275C2 (fr)
FR (1) FR2357004A1 (fr)
GB (1) GB1536530A (fr)
HK (1) HK36980A (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2632165B2 (de) * 1976-07-16 1978-06-01 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Regeln der Folgefrequenz von Taktimpulsen
US4212038A (en) * 1978-01-03 1980-07-08 Honeywell Information Systems Inc. Double density read recovery
US4245263A (en) * 1979-05-14 1981-01-13 Honeywell Information Systems Inc. Write precompensation and write encoding for FM and MFM recording
US4320465A (en) * 1979-05-14 1982-03-16 Honeywell Information Systems Inc. Digital frequency modulation and modified frequency modulation read recovery with data separation
US4298956A (en) * 1979-05-14 1981-11-03 Honeywell Information Systems Inc. Digital read recovery with variable frequency compensation using read only memories
US4415984A (en) * 1980-06-25 1983-11-15 Burroughs Corporation Synchronous clock regenerator for binary serial data signals
US5418936A (en) * 1990-12-14 1995-05-23 Dallas Semiconductor Corporation Double-buffered systems and methods
US5567993A (en) * 1994-06-23 1996-10-22 Dallas Semiconductor Corporation Programmable power supply system and methods
US5537360A (en) * 1994-09-16 1996-07-16 Dallas Semiconductor Corporation Programmable power supply systems and methods providing a write protected memory having multiple interface capability
US5959926A (en) * 1996-06-07 1999-09-28 Dallas Semiconductor Corp. Programmable power supply systems and methods providing a write protected memory having multiple interface capability

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518555A (en) * 1967-12-07 1970-06-30 Sanders Associates Inc Pulse train detectors
US3764989A (en) * 1972-12-20 1973-10-09 Ultronic Systems Inc Data sampling apparatus
US3787826A (en) * 1968-10-10 1974-01-22 Lockheed Electronics Co Split-phase adaptive decoding electronics

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3452348A (en) * 1965-06-29 1969-06-24 Rca Corp Conversion from self-clocking code to nrz code
JPS5040338B1 (fr) * 1968-12-04 1975-12-23
US3602828A (en) * 1969-10-27 1971-08-31 Ibm Self-clocking detection system
US3652943A (en) * 1970-05-04 1972-03-28 Honeywell Inc Apparatus including delay means for detecting the absence of information in a stream of bits
US3646451A (en) * 1970-08-07 1972-02-29 Bell Telephone Labor Inc Timing extraction circuit using a recirculating delay generator
US3684967A (en) * 1971-01-08 1972-08-15 Cogar Corp Automatic control of position and width of a tracking window in a data recovery system
US3740655A (en) * 1971-11-24 1973-06-19 Gen Electric Digital generation of quadrature samples
US3792361A (en) * 1972-08-23 1974-02-12 Itel Corp High speed data separator
US3761887A (en) * 1972-12-13 1973-09-25 Dayton Elec Prod Interval counting circuit and method
US3927259A (en) * 1974-02-13 1975-12-16 Atlantic Res Corp Signal identification system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518555A (en) * 1967-12-07 1970-06-30 Sanders Associates Inc Pulse train detectors
US3787826A (en) * 1968-10-10 1974-01-22 Lockheed Electronics Co Split-phase adaptive decoding electronics
US3764989A (en) * 1972-12-20 1973-10-09 Ultronic Systems Inc Data sampling apparatus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/72 *
EXBK/75 *

Also Published As

Publication number Publication date
AU506388B2 (en) 1979-12-20
FR2357004B1 (fr) 1985-03-15
AU2552777A (en) 1978-11-30
CA1073115A (fr) 1980-03-04
BE856032A (fr) 1977-10-17
JPS6235180B2 (fr) 1987-07-31
HK36980A (en) 1980-07-18
DE2728275C2 (de) 1986-10-09
GB1536530A (en) 1978-12-20
DE2728275A1 (de) 1978-01-05
US4034348A (en) 1977-07-05
JPS533210A (en) 1978-01-12

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