FR2354001A1 - Logic circuit receiving signal deflection or deviation - has compensator keeping constant propagation delay time including extended temp. range (NL 5.12.77) - Google Patents
Logic circuit receiving signal deflection or deviation - has compensator keeping constant propagation delay time including extended temp. range (NL 5.12.77)Info
- Publication number
- FR2354001A1 FR2354001A1 FR7716418A FR7716418A FR2354001A1 FR 2354001 A1 FR2354001 A1 FR 2354001A1 FR 7716418 A FR7716418 A FR 7716418A FR 7716418 A FR7716418 A FR 7716418A FR 2354001 A1 FR2354001 A1 FR 2354001A1
- Authority
- FR
- France
- Prior art keywords
- delay time
- propagation delay
- compensator
- range
- deviation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
- H03K19/0866—Stacked emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
Logic circuit has an input terminal (16) for signal deflection or deviation reception. A differential transistor circuit (10) responds to the input signal deflection etc., and causes a corresponding output signal change in response to internal signal generation in a specified propagation delay time. The transistor circuit (10) has energy supply terminals (VCC, VEE) to which a variable or unestablished voltage is applied. They are connected to a compensator (14), also connected to the input terminal (16), in order to keep constant the propagation delay time over the ambient temp. range.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69193076A | 1976-06-01 | 1976-06-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2354001A1 true FR2354001A1 (en) | 1977-12-30 |
FR2354001B1 FR2354001B1 (en) | 1980-02-01 |
Family
ID=24778554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7716418A Granted FR2354001A1 (en) | 1976-06-01 | 1977-05-27 | Logic circuit receiving signal deflection or deviation - has compensator keeping constant propagation delay time including extended temp. range (NL 5.12.77) |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS52147053A (en) |
DE (1) | DE2723386C3 (en) |
FR (1) | FR2354001A1 (en) |
NL (1) | NL173004B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0220454A1 (en) * | 1985-09-27 | 1987-05-06 | Siemens Aktiengesellschaft | Circuit arrangement for compensating gate transit time variations as a function of temperature |
EP0349824A2 (en) * | 1988-06-30 | 1990-01-10 | Fujitsu Limited | Integrated circuit having level converting circuit |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS579134A (en) * | 1980-06-18 | 1982-01-18 | Nec Corp | Logical circuit |
DE3043358A1 (en) * | 1980-11-17 | 1982-07-08 | Siemens AG, 1000 Berlin und 8000 München | Higher digital multiplex transmission - connecting up to four channels into multi-emitter transistor circuit |
JPS62222711A (en) * | 1986-03-11 | 1987-09-30 | Fujitsu Ltd | Latch circuit |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL6700144A (en) * | 1967-01-05 | 1968-07-08 | ||
US3522446A (en) * | 1967-08-31 | 1970-08-04 | Tokyo Shibaura Electric Co | Current switching logic circuit |
US3716722A (en) * | 1970-04-29 | 1973-02-13 | Cogar Corp | Temperature compensation for logic circuits |
-
1977
- 1977-05-24 DE DE19772723386 patent/DE2723386C3/en not_active Expired
- 1977-05-27 FR FR7716418A patent/FR2354001A1/en active Granted
- 1977-05-31 NL NL7705979A patent/NL173004B/en not_active Application Discontinuation
- 1977-05-31 JP JP6289777A patent/JPS52147053A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0220454A1 (en) * | 1985-09-27 | 1987-05-06 | Siemens Aktiengesellschaft | Circuit arrangement for compensating gate transit time variations as a function of temperature |
US4758740A (en) * | 1985-09-27 | 1988-07-19 | Siemens Aktiengesellschaft | Circuit for compensating the temperature dependence of gate transit times |
EP0349824A2 (en) * | 1988-06-30 | 1990-01-10 | Fujitsu Limited | Integrated circuit having level converting circuit |
EP0349824A3 (en) * | 1988-06-30 | 1990-07-25 | Fujitsu Limited | Integrated circuit having level converting circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS52147053A (en) | 1977-12-07 |
NL7705979A (en) | 1977-12-05 |
DE2723386C3 (en) | 1981-08-13 |
FR2354001B1 (en) | 1980-02-01 |
DE2723386B2 (en) | 1980-12-04 |
NL173004B (en) | 1983-06-16 |
DE2723386A1 (en) | 1977-12-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |