FR2316692A1 - Matrice adressable par cellule, tolerant les defauts - Google Patents

Matrice adressable par cellule, tolerant les defauts

Info

Publication number
FR2316692A1
FR2316692A1 FR7620501A FR7620501A FR2316692A1 FR 2316692 A1 FR2316692 A1 FR 2316692A1 FR 7620501 A FR7620501 A FR 7620501A FR 7620501 A FR7620501 A FR 7620501A FR 2316692 A1 FR2316692 A1 FR 2316692A1
Authority
FR
France
Prior art keywords
per cell
fault tolerant
matrix per
addressable matrix
addressable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7620501A
Other languages
English (en)
French (fr)
Other versions
FR2316692B1 (de
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/592,979 external-priority patent/US4047163A/en
Priority claimed from US05/593,090 external-priority patent/US4051354A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of FR2316692A1 publication Critical patent/FR2316692A1/fr
Application granted granted Critical
Publication of FR2316692B1 publication Critical patent/FR2316692B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
FR7620501A 1975-07-03 1976-07-05 Matrice adressable par cellule, tolerant les defauts Granted FR2316692A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/592,979 US4047163A (en) 1975-07-03 1975-07-03 Fault-tolerant cell addressable array
US05/593,090 US4051354A (en) 1975-07-03 1975-07-03 Fault-tolerant cell addressable array

Publications (2)

Publication Number Publication Date
FR2316692A1 true FR2316692A1 (fr) 1977-01-28
FR2316692B1 FR2316692B1 (de) 1982-10-08

Family

ID=27081591

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7620501A Granted FR2316692A1 (fr) 1975-07-03 1976-07-05 Matrice adressable par cellule, tolerant les defauts

Country Status (4)

Country Link
DE (1) DE2629893A1 (de)
FR (1) FR2316692A1 (de)
GB (1) GB1550675A (de)
NL (1) NL7607336A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2554622A1 (fr) * 1983-11-03 1985-05-10 Commissariat Energie Atomique Procede de fabrication d'une matrice de composants electroniques

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595497A (ja) * 1982-07-02 1984-01-12 Hitachi Ltd 半導体ｒｏｍ
GB2129585B (en) * 1982-10-29 1986-03-05 Inmos Ltd Memory system including a faulty rom array
JPH0670880B2 (ja) * 1983-01-21 1994-09-07 株式会社日立マイコンシステム 半導体記憶装置
JPS6199999A (ja) * 1984-10-19 1986-05-19 Hitachi Ltd 半導体記憶装置
KR910005601B1 (ko) * 1989-05-24 1991-07-31 삼성전자주식회사 리던던트 블럭을 가지는 반도체 메모리장치
GB8912866D0 (en) * 1989-06-05 1989-07-26 Code Masters Softwara Interfacing device for a computer games system
GB9305801D0 (en) * 1993-03-19 1993-05-05 Deans Alexander R Semiconductor memory system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2356167A1 (de) * 1973-11-09 1975-05-15 Horst Dipl Ing Henn Hochintegrierter festkoerperspeicher in ganzscheibentechnik

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2356167A1 (de) * 1973-11-09 1975-05-15 Horst Dipl Ing Henn Hochintegrierter festkoerperspeicher in ganzscheibentechnik

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2554622A1 (fr) * 1983-11-03 1985-05-10 Commissariat Energie Atomique Procede de fabrication d'une matrice de composants electroniques
US4676761A (en) * 1983-11-03 1987-06-30 Commissariat A L'energie Atomique Process for producing a matrix of electronic components

Also Published As

Publication number Publication date
DE2629893A1 (de) 1977-01-20
FR2316692B1 (de) 1982-10-08
GB1550675A (en) 1979-08-15
NL7607336A (nl) 1977-01-05

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