FR2315170A1 - Procede de fabrication de dispositifs mos complementaires sur substrat de saphir - Google Patents

Procede de fabrication de dispositifs mos complementaires sur substrat de saphir

Info

Publication number
FR2315170A1
FR2315170A1 FR7606043A FR7606043A FR2315170A1 FR 2315170 A1 FR2315170 A1 FR 2315170A1 FR 7606043 A FR7606043 A FR 7606043A FR 7606043 A FR7606043 A FR 7606043A FR 2315170 A1 FR2315170 A1 FR 2315170A1
Authority
FR
France
Prior art keywords
sapphire substrate
mos devices
complementary mos
manufacturing complementary
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7606043A
Other languages
English (en)
Other versions
FR2315170B3 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of FR2315170A1 publication Critical patent/FR2315170A1/fr
Application granted granted Critical
Publication of FR2315170B3 publication Critical patent/FR2315170B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR7606043A 1975-06-16 1976-03-03 Procede de fabrication de dispositifs mos complementaires sur substrat de saphir Granted FR2315170A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/587,465 US4002501A (en) 1975-06-16 1975-06-16 High speed, high yield CMOS/SOS process

Publications (2)

Publication Number Publication Date
FR2315170A1 true FR2315170A1 (fr) 1977-01-14
FR2315170B3 FR2315170B3 (fr) 1978-12-01

Family

ID=24349910

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7606043A Granted FR2315170A1 (fr) 1975-06-16 1976-03-03 Procede de fabrication de dispositifs mos complementaires sur substrat de saphir

Country Status (6)

Country Link
US (1) US4002501A (fr)
JP (1) JPS52183A (fr)
CA (1) CA1048654A (fr)
DE (1) DE2623015A1 (fr)
FR (1) FR2315170A1 (fr)
GB (1) GB1484834A (fr)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4097314A (en) * 1976-12-30 1978-06-27 Rca Corp. Method of making a sapphire gate transistor
US4070211A (en) * 1977-04-04 1978-01-24 The United States Of America As Represented By The Secretary Of The Navy Technique for threshold control over edges of devices on silicon-on-sapphire
US4217153A (en) * 1977-04-04 1980-08-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US4104087A (en) * 1977-04-07 1978-08-01 The United States Of America As Represented By The Secretary Of The Air Force Method for fabricating MNOS memory circuits
US4279069A (en) * 1979-02-21 1981-07-21 Rockwell International Corporation Fabrication of a nonvolatile memory array device
US4242156A (en) * 1979-10-15 1980-12-30 Rockwell International Corporation Method of fabricating an SOS island edge passivation structure
US4252574A (en) * 1979-11-09 1981-02-24 Rca Corporation Low leakage N-channel SOS transistors and method of making them
US4418470A (en) * 1981-10-21 1983-12-06 General Electric Company Method for fabricating silicon-on-sapphire monolithic microwave integrated circuits
US4399605A (en) * 1982-02-26 1983-08-23 International Business Machines Corporation Method of making dense complementary transistors
JPS5978557A (ja) * 1982-10-27 1984-05-07 Toshiba Corp 相補型ｍｏｓ半導体装置の製造方法
US4462151A (en) * 1982-12-03 1984-07-31 International Business Machines Corporation Method of making high density complementary transistors
US4470191A (en) * 1982-12-09 1984-09-11 International Business Machines Corporation Process for making complementary transistors by sequential implantations using oxidation barrier masking layer
US4751554A (en) * 1985-09-27 1988-06-14 Rca Corporation Silicon-on-sapphire integrated circuit and method of making the same
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
US4735917A (en) * 1986-04-28 1988-04-05 General Electric Company Silicon-on-sapphire integrated circuits
US4755481A (en) * 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
US5248623A (en) * 1988-02-19 1993-09-28 Nippondenso Co., Ltd. Method for making a polycrystalline diode having high breakdown
JP2653099B2 (ja) * 1988-05-17 1997-09-10 セイコーエプソン株式会社 アクティブマトリクスパネル，投写型表示装置及びビューファインダー
US4988638A (en) * 1988-11-07 1991-01-29 Xerox Corporation Method of fabrication a thin film SOI CMOS device
US5087580A (en) * 1990-09-17 1992-02-11 Texas Instruments Incorporated Self-aligned bipolar transistor structure and fabrication process
US5953582A (en) * 1993-02-10 1999-09-14 Seiko Epson Corporation Active matrix panel manufacturing method including TFTS having variable impurity concentration levels
US5300443A (en) * 1993-06-30 1994-04-05 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate
JPH08153879A (ja) 1994-11-26 1996-06-11 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
KR100226730B1 (ko) * 1997-04-24 1999-10-15 구본준 씨모스펫 및 그 제조방법
US6236089B1 (en) 1998-01-07 2001-05-22 Lg Semicon Co., Ltd. CMOSFET and method for fabricating the same
US6211045B1 (en) * 1999-11-30 2001-04-03 Vlsi Technology, Inc. Incorporation of nitrogen-based gas in polysilicon gate re-oxidation to improve hot carrier performance

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3484662A (en) * 1965-01-15 1969-12-16 North American Rockwell Thin film transistor on an insulating substrate
US3461361A (en) * 1966-02-24 1969-08-12 Rca Corp Complementary mos transistor integrated circuits with inversion layer formed by ionic discharge bombardment
US3636418A (en) * 1969-08-06 1972-01-18 Rca Corp Epitaxial semiconductor device having adherent bonding pads
US3745072A (en) * 1970-04-07 1973-07-10 Rca Corp Semiconductor device fabrication
US3749614A (en) * 1970-09-14 1973-07-31 Rca Corp Fabrication of semiconductor devices
US3796929A (en) * 1970-12-09 1974-03-12 Philips Nv Junction isolated integrated circuit resistor with crystal damage near isolation junction

Also Published As

Publication number Publication date
DE2623015A1 (de) 1977-01-20
FR2315170B3 (fr) 1978-12-01
US4002501A (en) 1977-01-11
GB1484834A (en) 1977-09-08
CA1048654A (fr) 1979-02-13
JPS52183A (en) 1977-01-05

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