FR2304991A1 - Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement - Google Patents

Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement

Info

Publication number
FR2304991A1
FR2304991A1 FR7602996A FR7602996A FR2304991A1 FR 2304991 A1 FR2304991 A1 FR 2304991A1 FR 7602996 A FR7602996 A FR 7602996A FR 7602996 A FR7602996 A FR 7602996A FR 2304991 A1 FR2304991 A1 FR 2304991A1
Authority
FR
France
Prior art keywords
circuits
arrangement
semiconductor memory
operating procedure
procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7602996A
Other languages
English (en)
Other versions
FR2304991B1 (fr
Inventor
Horst Berger
Klaus Heuber
Wilfried Klein
Knut Najmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19752511518 external-priority patent/DE2511518C3/de
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2304991A1 publication Critical patent/FR2304991A1/fr
Application granted granted Critical
Publication of FR2304991B1 publication Critical patent/FR2304991B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
FR7602996A 1975-03-15 1976-01-29 Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement Granted FR2304991A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752511518 DE2511518C3 (de) 1975-03-15 Verfahren und Schaltungsanordnung zum Betreiben eines Halbleiterspeichers

Publications (2)

Publication Number Publication Date
FR2304991A1 true FR2304991A1 (fr) 1976-10-15
FR2304991B1 FR2304991B1 (fr) 1979-04-06

Family

ID=5941550

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7602996A Granted FR2304991A1 (fr) 1975-03-15 1976-01-29 Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement

Country Status (4)

Country Link
US (1) US4090255A (fr)
JP (1) JPS51114036A (fr)
FR (1) FR2304991A1 (fr)
GB (1) GB1536013A (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2556833C3 (de) * 1975-12-17 1981-11-05 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Betreiben eines Halbleiterspeichers
DE2855866C3 (de) * 1978-12-22 1981-10-29 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers
DE2926050C2 (de) * 1979-06-28 1981-10-01 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Lesen Und/oder Schreiben eines integrierten Halbleiterspeichers mit Speicherzellen in MTL-Technik
DE2926094A1 (de) * 1979-06-28 1981-01-08 Ibm Deutschland Verfahren und schaltungsanordnung zum entladen von bitleitungskapazitaeten eines integrierten halbleiterspeichers
DE2929384C2 (de) * 1979-07-20 1981-07-30 Ibm Deutschland Gmbh, 7000 Stuttgart Nachladeschaltung für einen Halbleiterspeicher
DE2943565C2 (de) * 1979-10-29 1981-11-12 Ibm Deutschland Gmbh, 7000 Stuttgart Speicherzellennachbildung zur Referenzspannungserzeugung für Halbleiterspeicher in MTL-Technik
FR2469049A1 (fr) * 1979-10-30 1981-05-08 Ibm France Circuit comportant au moins deux dispositifs semi-conducteurs en technologie mtl presentant des temps de montee differents et circuits logiques en derivant
DE2944141A1 (de) * 1979-11-02 1981-05-14 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte speicheranordnung
DE2951945A1 (de) * 1979-12-22 1981-07-02 Ibm Deutschland Gmbh, 7000 Stuttgart Schaltungsanordnung zur kapazitiven lesesignalverstaerkung in einem integrierten halbleiterspeicher mit einem intergrierten halbleiterspeicher mit speicherzellen in mtl-technik
US4302823A (en) * 1979-12-27 1981-11-24 International Business Machines Corp. Differential charge sensing system
JPS594787B2 (ja) * 1979-12-28 1984-01-31 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 低インピ−ダンス感知増幅器を有し読取専用メモリ及び読取一書込メモリに共用可能なメモリ装置
US4404662A (en) * 1981-07-06 1983-09-13 International Business Machines Corporation Method and circuit for accessing an integrated semiconductor memory
US4555776A (en) * 1982-04-19 1985-11-26 International Business Machines Corporation Voltage balancing circuit for memory systems
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
EP0162934B1 (fr) * 1984-05-14 1989-11-08 Ibm Deutschland Gmbh Mémoire semi-conductrice
US4578779A (en) * 1984-06-25 1986-03-25 International Business Machines Corporation Voltage mode operation scheme for bipolar arrays
US4598390A (en) * 1984-06-25 1986-07-01 International Business Machines Corporation Random access memory RAM employing complementary transistor switch (CTS) memory cells
US4596002A (en) * 1984-06-25 1986-06-17 International Business Machines Corporation Random access memory RAM employing complementary transistor switch (CTS) memory cells
US4635228A (en) * 1984-12-17 1987-01-06 International Business Machines Corporation Random access memory employing unclamped complementary transistor switch (CTS) memory cells and utilizing word to drain line diode shunts
US4922455A (en) * 1987-09-08 1990-05-01 International Business Machines Corporation Memory cell with active device for saturation capacitance discharge prior to writing
US5200924A (en) * 1989-03-30 1993-04-06 Synergy Semiconductor Corporation Bit line discharge and sense circuit
US4991138A (en) * 1989-04-03 1991-02-05 International Business Machines Corporation High speed memory cell with multiple port capability
EP0426597B1 (fr) * 1989-10-30 1995-11-08 International Business Machines Corporation Schéma de décodage par bit pour réseaux de mémoire

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3505573A (en) * 1967-10-05 1970-04-07 Ibm Low standby power memory cell
US3540010A (en) * 1968-08-27 1970-11-10 Bell Telephone Labor Inc Diode-coupled semiconductive memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3067336A (en) * 1957-05-03 1962-12-04 Honeywell Regulator Co Bistable electronic switching circuitry for manipulating digital data
US3177374A (en) * 1961-03-10 1965-04-06 Philco Corp Binary data transfer circuit
US3292008A (en) * 1963-12-03 1966-12-13 Rca Corp Switching circuit having low standby power dissipation
US3363115A (en) * 1965-03-29 1968-01-09 Gen Micro Electronics Inc Integral counting circuit with storage capacitors in the conductive path of steering gate circuits
US3447137A (en) * 1965-05-13 1969-05-27 Bunker Ramo Digital memory apparatus
US3284782A (en) * 1966-02-16 1966-11-08 Rca Corp Memory storage system
US3518635A (en) * 1967-08-22 1970-06-30 Bunker Ramo Digital memory apparatus
US3588848A (en) * 1969-08-04 1971-06-28 Us Army Input-output control circuit for memory circuit
US3806898A (en) * 1973-06-29 1974-04-23 Ibm Regeneration of dynamic monolithic memories
DE2457921C2 (de) * 1974-12-07 1976-12-09 Ibm Deutschland Verfahren und schaltungsanordnung zur erhoehung der schreibgeschwindigkeit in integrierten datenspeichern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3505573A (en) * 1967-10-05 1970-04-07 Ibm Low standby power memory cell
US3540010A (en) * 1968-08-27 1970-11-10 Bell Telephone Labor Inc Diode-coupled semiconductive memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ARTICLE: "CURRENT STURING SIMPLIFIES AND SHRINKS IK BIPOLAR RAM" PAR GERSBACH *
REVUE US: "ELECTRONICS", VOL. 47, NO. 9, 2 MAI 1974, PAGES 110-114 *

Also Published As

Publication number Publication date
US4090255A (en) 1978-05-16
FR2304991B1 (fr) 1979-04-06
DE2511518A1 (de) 1976-09-16
DE2511518B2 (de) 1976-12-30
JPS51114036A (en) 1976-10-07
GB1536013A (en) 1978-12-13
JPS5751191B2 (fr) 1982-10-30

Similar Documents

Publication Publication Date Title
FR2304991A1 (fr) Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement
BE842511A (fr) Dispositif semi-conducteur et son procede de fabrication
FR2309036A1 (fr) Dispositif semiconducteur et son procede de fabrication
FR2298160A1 (fr) Memoire semi-conductrice
FR2317731A1 (fr) Memoire hierarchisee pour ordinateur
FR2282719A1 (fr) Support de circuits
SE7607216L (sv) Halvledaranordning
SE7602480L (sv) Halvledararrangemang for logikkretsar
DK479576A (da) Transistortendingskredslob
FR2301968A1 (fr) Circuit de traitement de signal
FR2316728A1 (fr) Test par faisceau electronique des circuits integres
BR7808124A (pt) Dispositivo semicondutor
FR2319978A1 (fr) Circuits integres semi-conducteurs et procede de preparation
FR2316730A1 (fr) Circuit logique integre et son procede de fabrication
FR2325194A1 (fr) Dispositif de pompage de charge pour semi-conducteur et son procede de fabrication
SE402839B (sv) Halvledaranordning och forfarande for dess framstellning
BR7604258A (pt) Meios de retardamento de sinais usando circuitos de memoria do cadeia de cacambas e de amostragem e retencao
FR2334205A1 (fr) Dispositif semi-conducteur et son procede de fabrication
SE406663B (sv) Reglerbart hallarorgan for integrerade kretsar
FR2312836A1 (fr) Circuit de cellules de memoire et son procede de fonctionnement
SE431913B (sv) Anordning for dimensionsmetning av kernbrenslekretsar
BR7800627A (pt) Dispositivo semicondutor
FR2321190A1 (fr) Composant semi-conducteur et son procede de fabrication
FR2304221A1 (fr) Circuit de memoire
SE7702969L (sv) Anordning for vermebehandling av finkornigt gods

Legal Events

Date Code Title Description
ST Notification of lapse