FR2289997A1 - Controleur de sequence d'acces pour une unite de memoire - Google Patents

Controleur de sequence d'acces pour une unite de memoire

Info

Publication number
FR2289997A1
FR2289997A1 FR7532450A FR7532450A FR2289997A1 FR 2289997 A1 FR2289997 A1 FR 2289997A1 FR 7532450 A FR7532450 A FR 7532450A FR 7532450 A FR7532450 A FR 7532450A FR 2289997 A1 FR2289997 A1 FR 2289997A1
Authority
FR
France
Prior art keywords
memory unit
sequence controller
access sequence
access
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7532450A
Other languages
English (en)
French (fr)
Other versions
FR2289997B1 (https=
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2289997A1 publication Critical patent/FR2289997A1/fr
Application granted granted Critical
Publication of FR2289997B1 publication Critical patent/FR2289997B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7532450A 1974-10-25 1975-10-23 Controleur de sequence d'acces pour une unite de memoire Granted FR2289997A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49122438A JPS5148937A (en) 1974-10-25 1974-10-25 Kiokusochi niokeru junjoseigyohoshiki

Publications (2)

Publication Number Publication Date
FR2289997A1 true FR2289997A1 (fr) 1976-05-28
FR2289997B1 FR2289997B1 (https=) 1981-08-07

Family

ID=14835840

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7532450A Granted FR2289997A1 (fr) 1974-10-25 1975-10-23 Controleur de sequence d'acces pour une unite de memoire

Country Status (5)

Country Link
US (1) US4293941A (https=)
JP (1) JPS5148937A (https=)
DE (1) DE2545873A1 (https=)
FR (1) FR2289997A1 (https=)
GB (1) GB1523755A (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725069A (en) * 1980-07-21 1982-02-09 Hitachi Ltd Vector data processing equipment
JPS58146969A (ja) * 1982-02-26 1983-09-01 Toshiba Corp インデツクス限定連続演算ベクトルプロセツサ
JPS5975365A (ja) * 1982-10-22 1984-04-28 Hitachi Ltd ベクトル処理装置
JPS59128670A (ja) * 1983-01-12 1984-07-24 Hitachi Ltd ベクトル処理装置
US4697235A (en) * 1983-03-22 1987-09-29 Fujitsu Limited List vector control apparatus
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
JPH077385B2 (ja) * 1983-12-23 1995-01-30 株式会社日立製作所 データ処理装置
JPS60134974A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd ベクトル処理装置
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
EP0167959B1 (en) * 1984-07-02 1992-05-06 Nec Corporation Computer vector register processing
FR2573888B1 (fr) * 1984-11-23 1987-01-16 Sintra Systeme pour la transmission simultanee de blocs de donnees ou de vecteurs entre une memoire et une ou plusieurs unites de traitement de donnees
US4890220A (en) * 1984-12-12 1989-12-26 Hitachi, Ltd. Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic operation results
JPS61173345A (ja) * 1985-01-29 1986-08-05 Hitachi Ltd 計算機システム
US4745547A (en) * 1985-06-17 1988-05-17 International Business Machines Corp. Vector processing
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4945479A (en) * 1985-07-31 1990-07-31 Unisys Corporation Tightly coupled scientific processing system
JPS6289149A (ja) * 1985-10-15 1987-04-23 Agency Of Ind Science & Technol 多ポ−トメモリシステム
JPS62120574A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd ベクトル処理装置
US4987534A (en) * 1986-08-20 1991-01-22 Nec Corporation Processor having synchronized operation between a CPU and a vector processor
EP0321493A4 (en) * 1986-08-22 1991-11-21 Commonwealth Scientific And Industrial Research Organisation A content-addressable memory system
JP2760790B2 (ja) * 1986-10-09 1998-06-04 株式会社日立製作所 データ処理装置
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5526487A (en) * 1989-02-09 1996-06-11 Cray Research, Inc. System for multiprocessor communication
US4951246A (en) * 1989-08-08 1990-08-21 Cray Research, Inc. Nibble-mode dram solid state storage device
JP3108421B2 (ja) * 1990-02-09 2000-11-13 シャープ株式会社 メモリアクセス装置
US7680990B2 (en) * 2003-05-30 2010-03-16 Hewlett-Packard Development Company, L.P. Superword memory-access instructions for data processor
US9639356B2 (en) * 2013-03-15 2017-05-02 Qualcomm Incorporated Arbitrary size table lookup and permutes with crossbar

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3405396A (en) * 1966-04-29 1968-10-08 Scient Data Systems Inc Digital data processing systems
US3439347A (en) * 1966-12-13 1969-04-15 Gen Electric Sub-word length arithmetic apparatus
US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing
US3602896A (en) * 1969-06-30 1971-08-31 Ibm Random access memory with flexible data boundaries
US3626374A (en) * 1970-02-10 1971-12-07 Bell Telephone Labor Inc High-speed data-directed information processing system characterized by a plural-module byte-organized memory unit
US3728686A (en) * 1971-06-07 1973-04-17 Rca Corp Computer memory with improved next word accessing
US3881173A (en) * 1973-05-14 1975-04-29 Amdahl Corp Condition code determination and data processing
FR122199A (https=) * 1973-12-17

Also Published As

Publication number Publication date
JPS5148937A (en) 1976-04-27
DE2545873A1 (de) 1976-05-06
FR2289997B1 (https=) 1981-08-07
GB1523755A (en) 1978-09-06
JPS5621173B2 (https=) 1981-05-18
US4293941A (en) 1981-10-06

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