FR2019679A1 - - Google Patents
Info
- Publication number
- FR2019679A1 FR2019679A1 FR6933490A FR6933490A FR2019679A1 FR 2019679 A1 FR2019679 A1 FR 2019679A1 FR 6933490 A FR6933490 A FR 6933490A FR 6933490 A FR6933490 A FR 6933490A FR 2019679 A1 FR2019679 A1 FR 2019679A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7111168 | 1968-10-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2019679A1 true FR2019679A1 (enExample) | 1970-07-03 |
| FR2019679B1 FR2019679B1 (enExample) | 1974-05-24 |
Family
ID=13451099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR6933490A Expired FR2019679B1 (enExample) | 1968-10-02 | 1969-10-01 |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1949174B2 (enExample) |
| FR (1) | FR2019679B1 (enExample) |
| GB (1) | GB1255347A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2477771A1 (fr) * | 1980-03-07 | 1981-09-11 | Philips Nv | Procede pour la realisation d'un dispositif semiconducteur a haute tension de blocage et dispositif semiconducteur ainsi realise |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3860461A (en) * | 1973-05-29 | 1975-01-14 | Texas Instruments Inc | Method for fabricating semiconductor devices utilizing composite masking |
| DE2658304C2 (de) * | 1975-12-24 | 1984-12-20 | Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa | Halbleitervorrichtung |
| DE2713647C2 (de) * | 1977-03-28 | 1984-11-29 | Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa | Halbleitervorrichtung, bestehend aus einem Halbleitersubstrat und aus einem Oberflächenschutzfilm |
| FI64878C (fi) * | 1982-05-10 | 1984-01-10 | Lohja Ab Oy | Kombinationsfilm foer isynnerhet tunnfilmelektroluminensstrukturer |
| JPH03198327A (ja) * | 1989-12-26 | 1991-08-29 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1969
- 1969-09-29 GB GB47743/69A patent/GB1255347A/en not_active Expired
- 1969-09-29 DE DE19691949174 patent/DE1949174B2/de active Pending
- 1969-10-01 FR FR6933490A patent/FR2019679B1/fr not_active Expired
Non-Patent Citations (2)
| Title |
|---|
| *REVUE AMERICAINE IBM TECHNICAL DISCLOSURE BULLETIN "VOL 8, AVRIL 66, PB-SI02 COMPOSITE LAYER AND METHODOF FORMING" R.P. ESETT ET AL. PAGE 1641.) * |
| REVUE BRITANNIQUE "SOLID STATE ELECTRONICS" VOL 11, JUILLET 68, "METAL NITRIDE-OXIDE SILICON FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED GATES" J.C. SARACE ET AL. PAGE 653-660 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2477771A1 (fr) * | 1980-03-07 | 1981-09-11 | Philips Nv | Procede pour la realisation d'un dispositif semiconducteur a haute tension de blocage et dispositif semiconducteur ainsi realise |
Also Published As
| Publication number | Publication date |
|---|---|
| DE1949174A1 (de) | 1970-05-14 |
| FR2019679B1 (enExample) | 1974-05-24 |
| DE1949174B2 (de) | 1971-09-23 |
| GB1255347A (en) | 1971-12-01 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |