FI964092A - Effektiv addressering av stora minnen - Google Patents

Effektiv addressering av stora minnen Download PDF

Info

Publication number
FI964092A
FI964092A FI964092A FI964092A FI964092A FI 964092 A FI964092 A FI 964092A FI 964092 A FI964092 A FI 964092A FI 964092 A FI964092 A FI 964092A FI 964092 A FI964092 A FI 964092A
Authority
FI
Finland
Prior art keywords
large memories
effective allocation
allocation
effective
memories
Prior art date
Application number
FI964092A
Other languages
English (en)
Finnish (fi)
Other versions
FI964092A0 (sv
Inventor
Paul W Dent
Original Assignee
Ericsson Ge Mobile Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Ge Mobile Inc filed Critical Ericsson Ge Mobile Inc
Publication of FI964092A publication Critical patent/FI964092A/sv
Publication of FI964092A0 publication Critical patent/FI964092A0/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Lubrication Of Internal Combustion Engines (AREA)
  • Vehicle Body Suspensions (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Memory System (AREA)
  • Microcomputers (AREA)
FI964092A 1994-04-13 1996-10-11 Effektiv addressering av stora minnen FI964092A0 (sv)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22713994A 1994-04-13 1994-04-13
PCT/US1995/004165 WO1995028677A1 (en) 1994-04-13 1995-04-13 Efficient addressing of large memories

Publications (2)

Publication Number Publication Date
FI964092A true FI964092A (sv) 1996-10-11
FI964092A0 FI964092A0 (sv) 1996-10-11

Family

ID=22851918

Family Applications (1)

Application Number Title Priority Date Filing Date
FI964092A FI964092A0 (sv) 1994-04-13 1996-10-11 Effektiv addressering av stora minnen

Country Status (8)

Country Link
US (2) US5680567A (sv)
EP (1) EP0755540B1 (sv)
JP (1) JPH10500790A (sv)
CN (1) CN1146249A (sv)
AU (1) AU682959B2 (sv)
DE (1) DE69530292T2 (sv)
FI (1) FI964092A0 (sv)
WO (1) WO1995028677A1 (sv)

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US6031767A (en) * 1996-09-18 2000-02-29 International Business Machines Corporation Integrated circuit I/O interface that uses excess data I/O pin bandwidth to input control signals or output status information
DE19638772A1 (de) * 1996-09-21 1998-03-26 Philips Patentverwaltung Telekommunikationsgerät, insbesondere Mobilfunkendgerät
US5822607A (en) * 1997-06-09 1998-10-13 Integrated Device Technology, Inc. Method for fast validation checking for code and data segment descriptor loads
US5815729A (en) * 1997-08-18 1998-09-29 Integrated Device Technology, Inc. Method and apparatus for on the fly descriptor validation
JP3161384B2 (ja) * 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置とそのアクセス方法
CA2217375C (en) * 1997-09-30 2001-09-11 Valerie Lines Bi-directional data bus scheme with optimized read and write characteristics
US6243798B1 (en) * 1997-10-28 2001-06-05 Microchip Technology Incorporated Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction
WO1999061988A1 (de) * 1998-05-26 1999-12-02 Siemens Aktiengesellschaft Verfahren zum zugriff auf einzeln adressierbare daten, datenverarbeitungssystem
US6571327B1 (en) * 1998-09-03 2003-05-27 Parthusceva Ltd. Non-aligned double word access in word addressable memory
US6480929B1 (en) 1998-10-31 2002-11-12 Advanced Micro Devices Inc. Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus
US6314504B1 (en) * 1999-03-09 2001-11-06 Ericsson, Inc. Multi-mode memory addressing using variable-length
JP2000315167A (ja) * 1999-04-30 2000-11-14 Toshiba Corp データ管理装置、計算機システムおよびプログラムを記憶した記憶媒体
US7155597B1 (en) * 1999-05-17 2006-12-26 Nxp B.V. Data processing device with aliased data pointer register
US6513094B1 (en) 1999-08-23 2003-01-28 Advanced Micro Devices, Inc. ROM/DRAM data bus sharing with write buffer and read prefetch activity
SG97920A1 (en) * 1999-10-18 2003-08-20 Ibm Address wrap function for addressable memory devices
EP1333380A1 (en) * 2002-01-30 2003-08-06 STMicroelectronics Limited DMA access generator
CN100338600C (zh) * 2003-01-03 2007-09-19 宇东科技股份有限公司 读取传感器的方法
DE10323415A1 (de) * 2003-05-23 2004-12-30 Infineon Technologies Ag Speicheranordnung
US7142479B2 (en) * 2004-04-19 2006-11-28 Nokia Corporation Addressing data within dynamic random access memory
US20060129701A1 (en) * 2004-12-15 2006-06-15 Shekoufeh Qawami Communicating an address to a memory device
JP2007172332A (ja) 2005-12-22 2007-07-05 Sanyo Electric Co Ltd メモリ制御回路及びメモリ制御方法
US8920343B2 (en) 2006-03-23 2014-12-30 Michael Edward Sabatino Apparatus for acquiring and processing of physiological auditory signals
US8656082B2 (en) * 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
US8811497B2 (en) * 2009-06-24 2014-08-19 Vixs Systems, Inc Processing system with register arbitration and methods for use therewith
US8738812B2 (en) * 2009-05-27 2014-05-27 Plx Technology, Inc. Transfer of commands and storage data to a data storage device
US8803214B2 (en) 2010-06-28 2014-08-12 Micron Technology, Inc. Three dimensional memory and methods of forming the same
US8759895B2 (en) 2011-02-25 2014-06-24 Micron Technology, Inc. Semiconductor charge storage apparatus and methods
US8972705B2 (en) * 2011-11-16 2015-03-03 Andes Technology Corporation Executing instructions for managing constant pool base register used for accessing constants during subroutine execution
CN103345448B (zh) * 2013-07-10 2016-01-06 广西科技大学 寻址与存储一体化两读出一写入存储控制器
CN110321295A (zh) * 2018-03-31 2019-10-11 深圳忆联信息系统有限公司 数据处理方法和装置
CN118012795A (zh) * 2024-01-30 2024-05-10 荟普智能装备(深圳)有限公司 Io通信方法、装置、设备以及存储介质

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US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4112490A (en) * 1976-11-24 1978-09-05 Intel Corporation Data transfer control apparatus and method
US4206503A (en) * 1978-01-10 1980-06-03 Honeywell Information Systems Inc. Multiple length address formation in a microprogrammed data processing system
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US4286321A (en) * 1979-06-18 1981-08-25 International Business Machines Corporation Common bus communication system in which the width of the address field is greater than the number of lines on the bus
US4403284A (en) * 1980-11-24 1983-09-06 Texas Instruments Incorporated Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address
US4479178A (en) * 1981-07-02 1984-10-23 Texas Instruments Incorporated Quadruply time-multiplex information bus
US4811202A (en) * 1981-10-01 1989-03-07 Texas Instruments Incorporated Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package
US4654781A (en) * 1981-10-02 1987-03-31 Raytheon Company Byte addressable memory for variable length instructions and data
JPS61175845A (ja) * 1985-01-31 1986-08-07 Toshiba Corp マイクロプロセツサシステム
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
JPS62110697A (ja) * 1985-11-08 1987-05-21 Nec Corp アドレス制御方式
JPS6356732A (ja) * 1986-08-27 1988-03-11 Nec Corp マイクロコンピユ−タシステム
JPS63179491A (ja) * 1987-01-21 1988-07-23 Hitachi Ltd アドレス制御装置
US4964037A (en) * 1987-02-27 1990-10-16 Bull Hn Information Systems Inc. Memory addressing arrangement
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JPH01120660A (ja) * 1987-11-04 1989-05-12 Nec Corp マイクロコンピュータ装置
US5151983A (en) * 1988-03-18 1992-09-29 Nec Corporation Microcomputer system with selectively bypassed memory output latches
US5212780A (en) * 1988-05-09 1993-05-18 Microchip Technology Incorporated System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory
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US5386523A (en) * 1992-01-10 1995-01-31 Digital Equipment Corporation Addressing scheme for accessing a portion of a large memory space

Also Published As

Publication number Publication date
AU682959B2 (en) 1997-10-23
EP0755540B1 (en) 2003-04-09
DE69530292D1 (de) 2003-05-15
WO1995028677A1 (en) 1995-10-26
JPH10500790A (ja) 1998-01-20
US5657288A (en) 1997-08-12
AU2278495A (en) 1995-11-10
CN1146249A (zh) 1997-03-26
EP0755540A1 (en) 1997-01-29
DE69530292T2 (de) 2003-12-04
FI964092A0 (sv) 1996-10-11
US5680567A (en) 1997-10-21

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