FI94699C - Method and circuit arrangement for generating a higher hierarchical level signal in a synchronous digital communication system - Google Patents

Description

- 94699

A method and circuit arrangement for generating a higher hierarchical level signal in a synchronous digital communication system.

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The invention relates to a method according to the preamble of appended claim 1 and a circuit arrangement according to the preamble of appended claim 3 for generating a higher hierarchical level signal in a synchronous digital communication system. The solution according to the invention is intended to be used in particular in devices belonging to the SDH system, but the invention is equally applicable to a corresponding American SONET system or any other similar system in which the frame structure consists of a predetermined number of constant length bytes.

In synchronous digital systems, such as the SDH system, a higher hierarchy level signal is generated by combining lower hierarchy level signals 20 in a time division manner. The content of the higher hierarchy level signal varies depending on what level and how it has been built. The STM-1 signal can thus include e.g. 3 TU-3 signals or 21 TU-2 signals or 63 TU-12 signals. In this presentation, the latter case is used as an example, where one upper hierarchy level signal, the STM-1 signal, contains 63 TU-12 signals.

When a higher hierarchy level signal includes a plurality of lower hierarchy level signals, the lower level sig-30 signals are mapped to the upper level frame using interleaving so that each lower level signal is • first bytes first, then second bytes, etc. Thus, STM-1 when the signal contains e.g. the above-mentioned 63 TU-12 signals, these 35 are located in the STM-1 frame so that first the first byte of the first TU-12 signal becomes • · - 94699 byte, etc. After the last byte of the 63rd TU-12 signal, the second byte of the first TU-12 signal comes again, etc. One line of the STM-5 1 frame (270 bytes in length) comes from each TU-12 four bytes from the signal and 4x9 = 36 bytes for the whole frame. The length of one complete TU-12 frame is 500 με, so it is basically divided into four consecutive STM-1 frames.

10 The frame structures briefly described above and the SDH system itself are described in more detail, for example, in Finnish patent application Fl-922657 and in the reference publications mentioned therein, to which reference is made for a more detailed description.

15 A general way of combining several signals on the same line to form a higher hierarchy level signal is illustrated in Figure 1 below. In this case, the connection is performed by a separate circuit or circuit board to which all lower level signals are applied to the inputs of the multiplexer 11, i.e. using the above example. TU-12 signals and. In the control unit 12, a control to the selection input of the multiplexer is established by means of the frame synchronization signal FSYNC and the clock signal CLK. The control word indicates which of the 25 input signals is currently selected for the output of the multiplexer.

The disadvantage of such a solution is that the connection has to be done with one (large) circuit, which, for example, if it breaks, prevents the passage of all signals.

30 Another common method is to implement multiplexing using ASICs (Application Specific Integrated Circuits) and three-state buffers. This option is illustrated in Figure 2 below. A higher hierarchy level signal, e.g. an STM-1 signal, is generated on the data bus DBUS (formed e.g.

- 94699 3 to the motherboard of the device), the bus of which is controlled by means of identical parallel circuit boards 21. Each circuit board has one or more ASICs 22, each of which forms one lower hierarchy level signal (channel) for the upper hierarchy level signal to be generated on the bus. Each ASIC circuit controls the bus (controlled by the clock signal CLK) with respect to the frame synchronization signal FSYNC in its own turn by means of its own three-state buffer 23. The advantage of this solution is that a single circuit-10 card can be removed from the device without disturbing the bus traffic (only the traffic of the time slots corresponding to that card is excluded). However, since each channel requires its own three-state buffer, a large number of conductors come into practice, e.g. in the case of 63 channels 63x8 15 conductors leaving the circuit boards (with a byte length of 8 bits). Another disadvantage of this solution is that it consumes a lot of power. In order to reduce the wires leaving the circuit board, the signals generated by the card can be multiplexed before they are connected to the bus 20, as shown in Figure 3 below. . The multiplek-25 Seri of each circuit board controls the common bus with respect to the DBUS frame synchronization signal FSYNC in its own turn by means of its three-state buffer 33.

One disadvantage of this solution is that the multiplexer circuit and the three-mode buffer take up a lot of space on each circuit board. Since in practice it is also desired to improve the reliability of the equipment by forming it from several parallel circuit boards, it further increases the space requirement as the number of multiplexers increases.

The multiplexer on the circuit board 21 can also be implemented by means of an internal bus, in the same way that the multiplexer operation was implemented in the embodiment of Fig. 2 by means of an external bus. Fig. 4 shows such an alternative, in which an internal bus 41 is formed on the circuit board 21, which is controlled by each ASIC circuit on the board with respect to the frame synchronization signal FSYNC in its own turn. In this case, a three-state buffer 42 is formed in each ASIC circuit, by means of which the ASIC circuit controls the internal bus 41. Each circuit board has one common three-state buffer 43, through which the internal bus 41 controls the external bus DBUS common to all cards.

The three-state buffer of each ASIC circuit is connected to a common AND gate 44, which provides control to the common three-state buffer 43, thus handling the circuit board control on the DBUS 15 bus.

The alternative shown in Figure 4 would be the best alternative to generating a higher hierarchy level signal if it did not have timing problems that require a practical doubling of the internal bus speed. This is because the timing differences of the ASICs are so large that there is a risk that two circuits will control the internal bus at the same time, causing the ASICs to break. In order to ensure that simultaneous control does not take place, the kel-25 lot frequency must be doubled, thus providing a safety interval between two consecutive controls. This in turn significantly increases the power consumption of the device. Clock frequency doubling is used in many different applications as well as in commercial circuits.

The object of the present invention is to overcome the drawbacks described above and to provide a method and a switching arrangement by means of which a signal of a higher hierarchy level can be generated as simply as possible. This object is achieved by a method and a coupling arrangement according to the invention.

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94699 5, the method being characterized by what is described in the characterizing part of the appended claim 1 and the circuit arrangement by what is described in the characterizing part of the appended claim 3.

The idea of the invention is to generate a higher hierarchy level signal by concatenating the circuits in which the lower hierarchy level signals are formed, and combining in the chain for each circuit the upper hierarchy level frame structure the data of the time slots corresponding to the channels formed in that circuit.

With the solution according to the invention, e.g. the following advantages: - The ASIC circuit does not require buffer circuits that are difficult to control, nor does it need to increase the clock frequency.

15 - No large multiplexer is required in each ASIC.

- Only one data bus leaves the circuit board.

- A broken circuit does not break parallel circuits.

- An additional 20 logic is not required in one ASIC.

The invention and its preferred embodiments will now be described in more detail with reference to Figures 5-8 in the accompanying drawings, in which Figure 1 shows the generation of a higher hierarchy signal in a known manner by one multiplexer circuit, Figure 2 shows the generation of a higher hierarchy signal in another known manner using 3 shows the generation of an upper hierarchy signal in a third known manner using one common multiplexer circuit per circuit board, Fig. 4 shows the generation of an upper hierarchy signal in a fourth known manner using 35 internal circuits of the circuit board, 94699 6 Figure 5 shows a basic switching arrangement according to the invention solution for one of the 5 ASIC circuits, Fig. 7 shows a counter used in the circuit of Fig. 6 and Fig. 8 is a timing diagram illustrating the operation of the members shown in Figs. 6 and 7.

Figure 5 shows a solution according to the invention, according to which the signal of the upper hierarchy level is formed by concatenation via ASIC circuits so that each circuit adds data of its own time slots to the frame to be transmitted. A single circuit board has M ASIC-15 circuits ASIC1, ASIC2, ... ASICM (different circuit boards may have different numbers of circuits), and a bus 51 divided by ASIC circuits is formed on the circuit board so that the bus passes from the first ASIC circuit in the chain (ASICM ) through each ASIC circuit to the last ASIC circuit 20 (ASIC1) of the chain, thus concatenating the ASIC circuits. The last ASIC circuit in the circuit is connected via a common three-state buffer 52 of the circuit board to control the external bus DBUS, for which a higher hierarchy level signal, in this example the payload portion of the STM-1 signal, is formed. In addition to the concatenable data CH_DATA, a concatenable enable signal CH_EN is transmitted between the ASICs in the chain, which is input from the last ASIC circuit in the chain (ASIC1) to control the common three-state buffer of the circuit board. As a three-state buffer, a transceiver structure of the totee-30 mic pole, open collector or open drain type, for example, can be used.

Figure 6 shows a solution according to the invention for one ASIC in a chain. First, each ASIC circuit has a synchronization unit 61 which multiplies 35 the sequence number of the ASIC circuit in question in the chain.

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94699 7 This unit receives its control information, for example, from the device's microprocessor (not shown), which supplies each ASIC circuit with its own (programmable) delay value D_SEL, which indicates the sequence number of the ASIC circuit in the chain.

5 In this example, a value of 4 is used for the last circuit in the chain (ASIC1), a value of 6 for the last previous (ASIC2), a value of 8 for the third (ASIC3), etc. The difference between the delay values of two consecutive ASICs is 2 (two clock cycles). and 72 10 (described below) delay in the chain.

Figure 7 shows in more detail the chain delay compensation in the synchronization unit 61. The delay value DSEL is applied to a counter 71 which continuously counts from zero to 9719 (the figure consists of having 15 time slots 270 in the STM-1 frame and nine TU-12 frames. corresponds to four STM-1 frames, i.e. 9x270x4 = 9720). The last ASIC circuit in the chain (ASIC1) loads the value 4 into the counter when it receives a synchronization pulse at its input LD. Correspondingly, the last previous ASIC circuit (ASIC2) 20 in the chain loads the value 6 into the counter when it receives a synchronization pulse at its input LD. By forming a circuit-specific phase difference with respect to the synchronization signal in this way, the different position of the ASIC circuits in the chain is compensated. The value of the counter is incremented with each clock pulse and when it reaches its maximum value of 25, the counter rotates to zero again.

Returning to Fig. 6, in the ASIC circuit, each TU-12 channel is formed in its own channel unit 62, thus there are N, while the ASIC circuit forms N TU-12 channels (N can be an arbitrary integer with 1 ... 63). The incoming data for the first channel unit 62 is denoted by R1DATA and the last by RNDATA. Corresponding clock signals are denoted by R1CLK and RNCLK. The data signals input to the channel units are typically 2048 • • »- 94699 8 kbit / s signals according to CCITT recommendations G.703 or G.704. Since the formation of TU-12 channels takes place as is known per se and is not related to the actual inventive idea, it will not be discussed further in this context.

The channel units 62 further receive a signal TU12_SYNC from the synchronization unit 61 indicating the location of the first TU-12 channel in the STM-1 frame and separating the different quarters of the TU-12 frame, and a signal TU12_EN indicating which STM-1 1-frame 10-row time slots belong to TU-12 channels. In addition, each channel unit 62 receives a 6-bit control word SLOTX (X = 1 ... N) from the device's microprocessor, which tells the channel unit which TU-12 time slot it is allowed to use. According to this, the channel unit generates its own enable signal SLX_EN 15 (X = 1 ... N). These signals are connected to the encoder 64, already at its own input (0 ... N). For the multiplexer 65, the encoder encodes an enable signal which is applied to the selection input SEL of the multiplexer. This enable signal determines which signal at the input of the multiplexer is currently selected at the output of the multiplexer.

Thus, the multiplexer 65 combines the channels to be established by its own ASIC circuit so that the multiplexer selects the data of the channel 2 5 declared active at its output in each time slot (by means of the enable signal).

The second multiplexer 74 of the ASIC circuit combines the data of the channels from its own ASIC circuit with the data of the channels formed in the previous ASIC circuits of the chain. To this end, the output signal of the first multiplexer 65 is input to the first input of the second multiplexer 74 (input 1) and the ket-judata CH_DATA to be received from the bus 51 via the register 70 formed by the D-flip-flop to the second input of the second multiplexer 74 (input 0). The multiplexer 74 selects for its output either chain data 35 or one of the channels of its own ASIC circuit (channel data).

• · 94699 9

It should be noted that the first circuit of the chain does not require D-flip-flops 69 and 70, an OR gate 68 or a multiplexer 74. If the circuits are implemented as ASIC circuits, said circuit elements are in the circuit but are disabled.

5 Each channel unit 62 has a signal SLX_EN

(X = 1 ... N) connected to the corresponding input of the OR gate 67 with N inputs, whereby the output of the OR gate 67 provides information if one of the TU-12 channels is active. The output of the OR gate is connected directly to the selection input of the second multiplexer 74, this signal prioritizing the transmission of data from its own ASIC circuit over the transmission of chain data CH_DATA. The output of the OR gate 67 is further connected to the first input of the second OR gate 68. Connected to the second input of the OR gate 68 is a ket-juenable signal CH_EN from the register 69 formed by the D-flip-flop (cf. Fig. 5), which is input from the previous ASIC circuit to the input D of the register 69. The second OR gate 68 connects the previous To the 20 chainable signals generated by the SLOTX_EN signals generated by the ASIC circuits, the SLOTX_EN signals generated by the ASIC circuit. The combined signal is coupled from the output of register 71 formed by D-flip-flop to either the next ASIC circuit in the chain (register D input D 69), in which case it is represented as CH_EN, or, if the last ASIC circuit in the chain is in question, to control the common three-state buffer 52 it is shown as signal STM-1_EN.

Figure 8 illustrates the timing of concatenation as an example for a few time slots. Fig. 30 shows at the top the synchronization signal FSYNC (which in this case has a frequency of 2.0 kHz, corresponding to the frequency of one TU-12 frame). In this case, it is shown to form the second, fourth, sixth and seventh TU-12 channels of the STM-1 frame, which in this example 35 are formed so that the second and seventh TU-12 channels - 94699 10 are formed in the second last ASIC of the chain ( ASIC2), and the fourth and sixth TU-12 channels in the last ASIC circuit of the chain (ASIC1). (Note that in the STM-1 frame, each line first has a total of 18 header area bytes and padding bytes, with the TU-12 channels only starting at counter 18. In this case, the AU-4 pointer is selected to indicate a fixed position 522. ) Second, for the last ASIC, the first and fourth channel units 10 (signals SL1_EN and SL4_EN) are randomly selected, and for the last ASIC, the first and second channel units (signals SL1_EN and SL2_EN) are selected. The horizontal line, preceded by the reference mark 71:, shows the readings of the counter 71. As can be seen from the figure, the counter of the last ASIC circuit in the chain has a value of 4 after the synchronization pulse, and the counter of the second last ASIC circuit of the chain (ASIC2) has a value of 6. Considering that the enable signals generated in the ASIC2 circuit pass through a total of three from the register (cf. Fig. 6) before they appear at the output of the last ASIC circuit of the chain 20 and the enable signals generated in the circuit ASIC1, respectively, pass through one register, the STM-1_EN signal according to the figure is obtained at the output of the last ASIC circuit (for these time slots). The outgoing upper hierarchy level signal STM-1 25 OUT thus provides the first, four, six and seven bytes (VI bytes) of the TU-12 channels.

In Fig. 8, the operation was illustrated only for the two, four, six and seven channels of the TU-12, in reality the operation is similar for all the channels 30, forming a complete payload part of the STM-1 signal. The final STM-1 signal is obtained by adding the header bytes of the VC-4 frame and the header bytes of the STM-1 frame with the AU-4 pointer. This addition can be made in the last circuit of the chain or in later stages.

35 Since the addition is made as is known per se and is not related to the actual inventive idea of li 94699 11, it will not be described in more detail in this context.

If it is not desired to establish all hal-12 channels on the same circuit board 21, but to increase the reliability of the device 5 by establishing channels on more than one parallel circuit board, as shown in Figure 5, the situation is quite similar, but the three-mode buffer of each circuit board controls the external bus in the corresponding time slots. the channels are formed by a ky-10 standing circuit board. The upper hierarchy signal is thus only finally generated on the external bus DBUS.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified in many ways within the scope of the inventive idea set forth above and in the appended claims.

For example, the circuit board can be implemented, instead of the traditional circuit board technique, using MCM or a similar technique 20 (MCM, Multichip Module). The separate circuit 22 may in turn be an ASIC circuit or a commercially available IC circuit or a unit implemented with MCM or circuit board technology. The terms circuit and circuit board must therefore be understood in a broader sense to encompass the alternatives described above.

Claims (5)

A method for generating an upper hierarchy signal in a synchronous digital communication system, the method comprising - generating a plurality of lower hierarchy signals with separate circuits (22), and - generating a higher hierarchy signal by combining a plurality of lower level signals into a single upper level signal. that - said separate circuits (22) are daisy-chained by means of a common bus (51) into a chain in which said bus connects the separate circuits (22), 15. in each circuit (22) the data of the channels to be formed on said circuit are added to the time slots of the upper hierarchy frame; in other circuits to the data of channels already possibly added, and 20. the generated signal is switched forward from the circuit at the end of the chain. Method according to claim 1, characterized in that the upper hierarchy level signal is generated by at least two separate circuits (22) in the circuit board account (21) such that all the circuit boards control a common external bus (DBUS) to which the final upper hierarchy level signal is generated. . A circuit arrangement for generating an upper hierarchy level signal 30 in a synchronous digital communication system, the circuit arrangement comprising separate circuits (22) for generating a plurality of lower hierarchy level signals, characterized in that - said separate circuits (22) are daisy-chained by a common bus (51) connecting said circuits to each other, - each circuit (22) comprises adding means (67, 74) for adding the data of the channels to be formed on said circuit to the time slots of the upper hierarchy level frame corresponding to these channels 5, among other channels already added in other circuits in the chain, and - the circuit arrangement further comprises means (52) for forwarding the generated signal from the circuit (22) at the end of the chain. A circuit arrangement according to claim 3, characterized in that said means comprise a three-state buffer (52) driving an external bus (DBUS). A circuit arrangement according to claim 4, characterized in that it comprises a plurality of parallel circuit boards (21), wherein the three-state buffer of each circuit board drives an external bus (DBUS). > · J »I · 14 94699