FI94811B - A method and apparatus for aligning signal frames used in a synchronous digital communication system - Google Patents

Description

5,94811

A method and apparatus for aligning signal frames used in a synchronous digital communication system

The invention relates to a method according to the preamble of appended claim 1 and to an apparatus according to the preamble of appended claim 6 for aligning signals used in a synchronous digital telecommunication system. The solution according to the invention is intended in particular for repeater devices of a synchronous digital communication system, but it can in principle be applied in any network element of the system where there is a need to align two or more signals of the same hierarchy level.

The current digital transmission network is plesiochronous, which means that, for example, each 2 Mbit / s basic channelization system has its own clock, independent of other systems. As a result, it is not possible to locate one 2 Mbit / s signal from the bit stream of the upper ·: 20 degree system, but to separate the 2 Mbit / s signal, the higher level signal must be demultiplexed to 2 Mbit / s through each intermediate stage. As a result, it has been particularly expensive to build branched connections that require multiple multiplexers and demultiplexers. Another disadvantage of a plesiochronous transmission network is that devices from two different device manufacturers are often not compatible with each other.

Among other things, the above-mentioned shortcomings have led to the definition of 30 new Synchronous Digital Hierarchies (SDHs). The definition has been made e.g. CCITT Recommendations G.707 to G.709 and G.781 to G.784. The synchronous digital hierarchy is based on STM-N transport frames (Synchronous Transport Module), which exist at several 35 hierarchical levels N (N = 1, 4.16 ...). Existing PCM systems, such as 2 94811 systems, such as 2, 8, and 34 Mbit / s systems, are multiplexed into a synchronous 155.520 Mbit / s frame at the lowest level (N = 1) of the SDH hierarchy, referred to above as the STM system. l-frame. At the higher levels of the hierarchy 5, the bit rates are multiples of the lowest level. In principle, all nodes in a synchronous transmission network are synchronized to a single clock. However, if some nodes lost connection to a common clock, it would lead to difficulties in connections between nodes. At reception, the phase of the frame 10 must also be able to be easily determined. For the above reasons, an indicator has been introduced in SDH communication, which is a number indicating the phase of the payload within a frame, that is, the pointer points to the byte in the STM frame from which the payload begins.

Figure 1 illustrates the structure of an STM-N frame, and Figure 2 illustrates one STM-1 frame. The STM-N frame consists of a matrix with 9 rows and N times 270 columns so that there is one byte at the intersection of the column in each row. Rows 1- * of the first column of N x 9! 20 3 and 5-9 comprise a header area SOH (Section OverHead), and line 4 an AU pointer. The remainder of the frame structure is N times the 261 column length portion that includes the payload portion of the STM-N frame.

Figure 2 illustrates one STM-1 frame, 25 rows of which is thus 270 bytes in length as described above. The payload part comprises one or more administration units AU (Administration Unit). In the example case of the figure, the payload part consists of an AU-4 unit, in which a virtual container VC-4 (Virtual 30 Container) is placed, respectively. (Alternatively, the transmission frame STM-1 may contain three AU-3 units, each of which is housed in a corresponding virtual container VC-3). The VC-4, in turn, consists of a one-byte (9 bytes in total) path header (PathOverHead) at the beginning of each line and 35 payload sections, the lower level frames of which 3,94811 also contain bytes that allow connection equalization when mapping the information signal to be mapped. degree of name value.

5 Each byte in the AU-4 has its own slot number. The above-mentioned AU pointer contains the location of the first byte of the VC-4 container in the VC-4 unit. Pointers can be used to perform positive or negative pointer alignments at different points on the SDH network. If a virtual container with a higher clock frequency than the recent one is brought in from a node in the network 10 operating at a certain clock frequency, the data buffer will be filled. In this case, a negative equalization must be performed: one byte (3 bytes in the case of VC-4 container 15 bytes) is transferred from the received VC container to the header state side of the frame to be transmitted, and the pointer value is decremented accordingly by one. On the other hand, if the received VC container has a lower speed than the node clock speed, the data buffer tends to empty. In this case, a positive alignment must be performed: “A fill byte is added to the 20 VC containers to be sent (3 bytes in the case of a VC-4 container) and the value of the pointer is increased by one.

Figure 3 shows how it is possible to form an STM-N frame from existing bitstreams. These bit-25 streams (1.5, 2, 6, 8, 34, 45 or 140 Mbit / s, shown * on the right in the figure) are packed in the first step in containers C (Container) defined by CCITT. In the second step, header bytes containing control information are added to the containers to obtain the virtual container VC-11, VC-12, VC-2, VC-3 or VC- shown above. 4 (of the indices after the abbreviations, the first refers to the hierarchy level and the second to the bit rate). This virtual container remains intact on its journey through the synchronous network all the way to the destination of the container.

35 Virtual containers are further formed (depending on the level of the hierarchy 4,94811) into either the so-called subunits TU (Tributary Unit) or the above AU units (AU-3 and AU-4) by adding pointers. The AU can be mapped directly to the STM-1 frame, but the TUs must be assembled through sub-5 unit groups TUG (Tributary Unit Group) and VC-3 and VC-4 units to form AUs, which can then be mapped to the STM -L-frame. In Figure 3, mapping is indicated by a solid thin line, aligning by a dashed line, and multiplexing by a solid thicker line.

As can be seen from Figure 3, there are several alternative ways of forming the STM-1 frame, as well as, for example, the contents of the top-level virtual container 15 VC-4 may vary depending on the level and how it has been started. The STM-1 signal may thus include, for example, 3 TU-3 units or 21 TU-2 units or 63 TU-12 units, or some combination of these. When a higher level unit contains several lower ** · 20 level units, eg when a VC-4 unit contains, for example, TU-12 units (there are thus a total of 63 units in one VC-4 unit, cf. Figure 3), there is a lower level the units are mapped to the upper level frame using interleaving so that the first bytes are taken first from each of the lower level 25 units, then the second bytes, etc. The example of Figure 2 shows how the VC-4 unit first takes all 63 bytes. The first bytes of the TU-12, followed by the second bytes of all 63 TU-12, etc.

30 Because the SDH frame structures described above are not included. within the scope of the actual inventive idea, as well as the formation of these frame structures, they will not be described further in this context. SDH frame structures and their formation are described, for example, in references 35 [1] and [2], which are referred to for a more detailed description.1 SU S-Hill M I R1: 1 5 94811 (reference list is at the end of the explanatory note).

The alignment of several signals in the same hierarchy level (cf. Fig. 3) is usually performed with pointer operations, but e.g. in repeater devices pointer speeds are not allowed to be performed, but only the STM-1 frame string header RSOH (Regenerator Section OverHead) can be processed. If pointer operations cannot be used for alignment, alignment could be performed, for example, as a shift register type solution by adjusting the delays of different signals. However, such a solution places quite strict requirements on the tolerances of the characteristics of the clock signal, such as, for example, jitter.

It is an object of the present invention to provide a method and apparatus which does not place great demands on the clock signal used and which allows signals of the same hierarchy level to be aligned with each other in the simplest possible way, i.e. without constantly monitoring the phase of the outgoing and incoming signals. This object is achieved by a method according to the invention and a device according to the invention, the method being characterized by what is described in the characterizing part of the appended claim 1 and the device by what is described in the characterizing part of the appended claim 6.

The idea of the invention is to adjust the storage time of each signal in the buffer on the basis of the phase differences indicated by the delay measurement starting from a certain t phase of the frame so that the signals are aligned with each other. Although the adjustment is made in steps determined by the period of the read clock signal 30, the recording time is still not tied to whole clock periods, because the phase of the write clock • * may slide relative to the read clock.

In the following, the invention and its preferred embodiments will be described in more detail with reference to the examples of the accompanying Figures 4-635 in the accompanying drawings, in which 6 94811 Figure 1 shows the basic structure of one STM-N frame, Figure 2 shows the structure of one STM-1 frame; N-frame generation from existing PCM systems, Fig. 4 shows a block diagram of an STM-4 node of a synchronous digital communication system, Fig. 5 shows the alignment circuitry of the STM-4 unit shown in Fig. 4, and Fig. 6 shows a more detailed block diagram of one of the STM-4 units shown in Fig. 5. the alignment.

Figure 4 shows an STM-4 node of an SDH network comprising a plurality of parallel STM-1 signals from the interface unit 41, each of which receives (first transmission direction) an STM-1 signal from fiber 42 and transmits (second transmission direction) an STM-1 signal to the fiber. In the STM-4 unit 43, an STM-4 signal is generated for the fiber 44 from the received STM-1 signals, and four STM-1 signals for the fibers 42 are separated from the STM-4 signal from the fiber 44, respectively.

20 This presentation considers the first direction of transmission mentioned above.

The interface unit 41 converts the STM-1 signals into electronic form and forwards them along the internal bus B of the node to the STM-4 unit 43, which further generates an STM-4 signal from them. The problem in such a situation is the delays of the internal bus B, which are different for each STM-1 signal. Thus, although the interface units send STM-1 signals to the bus (usually implemented on the backplane of the device) at the same edge of the clock signal, they arrive at the STM-4 unit at slightly different times.

. (This is partly due to the different propagation delay of the already mentioned clock signal to the different interface units.)

Due to the transit time differences referred to above, the frames of the incoming STM-1 signals must be aligned in the STM-4 unit 43. This is done by the alignment circuit 50 according to the invention shown in Fig. 5, which comprises four parallel alignment circuits 51, which are separated from each other in the figure by numbering them with reference numerals # 1- to # 4. For each alignment circuit, an STM-1 utility signal D, a frame synchronization signal FS and a clock signal CLK1 are supplied from the interface circuit 5. To perform the alignment, one of the alignment circuits 51, in this case circuit 1, outputs a frame pulse A1 after a delay period measured from a certain phase, the occurrence of which is used relative to the other alignment circuits (# 2- # 4) as a reference for performing the alignment. To this end, the reference signal A1 provided by the alignment circuit # 1 is connected to all other alignment circuits 51. Due to the different position of the alignment circuit # 1, it is hereinafter referred to as the master circuit and the other alignment circuits (# 2- # 4) as slaves.

When the alignment of the STM-1 signals is performed at the input of the STM-4 unit 43 in accordance with the invention, the data is further coupled to the pointer generation and multiplexing circuits of the STM-4 unit to generate an STM-4 signal in a manner known per se by byte interleaving from four STM-1 signals. However, since this is no longer within the scope of the idea of the invention, these circuits will not be described in this context.

Figure 6 is a block diagram showing a more detailed structure of one of the alignment circuits 51. The alignment circuit comprises a flexible buffer 61, of which only the output side (read side) is shown in Fig. 6, for assigning a read address of the read address counter 62 to the flexible buffer, a delay counter-disc 60 which measures the delay from a certain phase of the frame and adjusts the »* read address and multiplexer. 64 for selecting the correct signal for the read address counter 62 in each alignment circuit.

In the alignment circuit 51, the incoming data D is written to a flexible buffer 61, from which it is further read by the means shown in Fig. 6. In addition to the data, information about the phase of the frame is stored in the buffer. This signal is indicated in the figure by the reference symbol FS, and can in principle indicate any point in the frame, as long as that point is the same for all signals to be targeted.

The synchronization pulse FS starts the alignment process according to the invention in each alignment circuit by starting the delay counter 63 while reading (alongside the data) out of the buffer 61. After a predetermined delay period, when the delay counter 63 has reached a predetermined reading, the delay counter , 2, 3 or 4). The master circuit 15 (n * 1) passes this reference pulse A1 via the multiplexer 64 to the first input REF of the read address counter 62. Thus, the master circuit has a branch from the delay counter 63 selected in the multiplexer 64. In addition, the reference pulse A1 of the master circuit is applied to other alignment silicon-20s (# 2- # 4), as shown in Fig. 5.

At the time of the occurrence of the reference pulse AI, the increment value of the read address CV is obtained from the reading of the delay counter 63. This value is loaded from the second output of the delay counter at the rising edge of the clock signal 25 CLK2 following that occurrence to the control input INC1 of the increment step of the read address counter 62. The new read address, which is connected to the read address input RA of the flexible buffer, is obtained by adding the old address value CV with the delay counter value CV at the time of occurrence of the 30 reference pulses A1 (the value CV can also be negative, in which case we speak of the decryption value).

In order to make the solution as simple as possible, it is advantageous for the delay counter to give a reference pulse 35 when its read CV is +1. Since the master circuit 9 94811 feeds back the reference pulse to the circuit's own read address counter, the read address counter of the master circuit steps normally in this case as well (the increment step is one unit).

5 Other alignment circuits (so-called slave circuits # 2- # 4) select the signal from the input line L1 to the output by the multiplexer 64. A reference signal A1 from the master circuit is connected to this input line, which is connected to the reference input 10F of the alignment circuit read address counter 62. In this case, the value CV of the delay counter obtained as the increment / decrement value of the read address counter at the moment of the reference pulse differs from the increment value of the master circuit according to the phase difference of the corresponding STM signals. The increment / decrement value provided by the delay counter thus adjusts the time interval between the writing to the flexible buffer and the reading from the flexible buffer (i.e., adjusts the length of time the data is stored in the flexible buffer). In this way, the phase 20 of each signal can be adjusted with respect to the signal phase of the master circuit so that the frames of all signals become aligned with each other (the same phase). It should also be noted that the alignment is performed automatically once per frame as described above, initiated by the frame synchronization signal FS, and that the read address counter otherwise counts normally forward (increment step is +1) at the rising edges of the clock signal CLK2 connected to its clock input C. ).

30 The alignment circuits shown above are as identical as possible. Of course, it would be possible to build the master circuit more clearly than slave circuits, in which case, for example, there would be no multiplexer at all and the input line • LI would only be on slave circuits. However, the embodiment described above is advantageous in that the master and sledge circuits differ only in the switching of the reference pulse and the control of the multiplexer. Thus, even if the delay counters of the slave circuits also give a reference pulse after reaching a certain predetermined value, these reference pulses are not functionally connected to anything.

The delay counters 63 may be, for example, four-bit count-down counters, the calculation range of which is such that the above-mentioned value +1 occurs approximately in the middle of the calculation range (e.g. the calculation range 7.6 ... 0, -1, -2 ...- 7). Of course, it is advantageous to take a value of +1 as the value of the delay counter corresponding to the moment of occurrence of the reference pulse, since it corresponds to the normal increment value of the read address counter. On the other hand, it is advantageous to list that the value +1 occurs approximately halfway through the calculation range, because the signals of the slave circuits may be either behind or above the signal of the master circuit.

For example, if the calculation range described above is used and the value of the delay counter of the slave circuit is one of the values 7.6 ... 2, the signal of the 20 slave circuits lags behind the signal of the master circuit, whereby the the reading and writing of the signal must be adjusted closer in time. Correspondingly, if the value of the delay counter of the slave circuit is one of the values o ...— 7, the signal of the slave circuit is above the signal of the master circuit, whereby 25. the reading and writing of the signal must be adjusted farther apart. After alignment, a value of +1 is obtained from all delay counters at the time the reference pulse occurs.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified within the scope of the inventive idea set forth above and in the appended claims. Although the invention has been described above specifically as an example related to an SDH system, the solution according to the invention is naturally applicable to any corresponding system, e.g. a SONET system. Although the invention has further been described with reference to an STM-1 level signal, it is clear that the invention can be applied to the alignment of signals at any hierarchical level.

Reference list: [1]. CCITT Blue Book, Recommendation G.709: "Synch-10 ronous Multiplexing structure", May 1990.

[2]. SDH - New digital hierarchy, TELE 2/90.

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Claims (9)

12,94811 A method for aligning frames of signals used in a synchronous digital communication system, such as an SDH or SONET system 5, which signals have a frame structure consisting of a predetermined number of constant length bytes stored according to the method in a flexible buffer (61), characterized in that 10 - at the same stage of each signal frame, a delay measurement is started, - after a certain predetermined delay period, a reference signal (AI) is given for the delay measurement associated with one signal to be targeted, the 15th value (CV) indicated by the delay measurement associated with each signal to be targeted at the occurrence of said reference signal, for the corresponding target signal, a read address for reading from said flexible buffer (61), v - 20 Method according to claim 1, characterized in that the delay measurement is performed by a delay counter (63) which is started in the same phase of each signal frame. A method according to claim 2, characterized in that the read addresses are formed by a counter (62) by incrementing / decrementing the counter by a value which depends on the value (CV) of the delay counter (63) at the time of the reference signal. Method according to Claim 3, characterized in that the value which the delay counter (63) has at the time of the occurrence of the reference signal is used directly as the increment / decrementing value of the read address counter. A method according to claim 2, characterized in that said reference pulse (AI) is provided substantially halfway between the calculation area of the delay counter (63). An apparatus for aligning frames of signals used in a synchronous digital communication system, such as an SDH or SONET system, which signals have a frame structure consisting of a predetermined number of constant length bytes, the apparatus comprising a flexible buffer (61) for storing signals and each signal to be aligned towards a read address-10 counter (62) for generating a read address for said flexible buffer (61) for reading said signal from the buffer (61), characterized in that it comprises - timing means (63) associated with each signal to be targeted for initiating a delay measurement at a certain stage of each target signal frame; at least one of the means comprises pulse generating means (63) for transmitting a reference pulse (AI) after a predetermined delay period, and - address generating means (62) associated with each signal to be applied to each n for generating a read address associated with the signal to be applied for reading from the flexible buffer (61), the read address being formed from the value (CV) indicated by the delay measurement associated with said signal at the time of said reference pulse (A1). Device according to claim 6, characterized in that the time measuring means comprise a delay counter (63), wherein the first output of one delay counter is connected to said addressing means 30 for providing a reference pulse (AI) for addressing associated with each signal. Device according to claim 7, characterized in that the addressing means comprise an address counter (62) to which the second output of said delay counter (63) 35 is operatively connected to provide an increment / decrement value to the address counter (62). 14 94811 Device according to claim 8, characterized in that the first output of said one delay counter is connected to each address counter (62) via a multiplexer (64). > * 4 • · „94811