FI93290C - Method and apparatus for transmitting an asynchronous signal to a synchronous system - Google Patents

Description

93290

A method and apparatus for transferring an asynchronous signal to a synchronous system

The invention relates to a method according to the preamble of appended claim 1 and to an apparatus according to the preamble of appended claim 4 for transmitting an asynchronous signal to a synchronous system.

The solution according to the invention makes it possible to connect asynchronous devices to synchronous devices or to synchronous transmission systems. Such asynchronous devices can be, for example, modems, computers and computer terminals, various measuring devices or printers. It is particularly known to use modems for communication between computers via telephone lines. At the transmitting end, the modem modulates the carrier and sends the modulated signal to the telephone line. At the receiving end, the second modem demodulates the received signal into an original data signal so that the receiving computer can process the data. Between the transmission and reception ends, the asynchronous signal transmitted by the modem is transmitted in a synchronous transmission system, such as a PCM system. By synchronous device or transmission system is meant a device or system in which the transmission takes place synchronously, i.e. in such a way that there are always an integer number of time interval units between the two significant moments of the signal.

Prior art solutions generally operate by first separating the start and stop bits 30 (start and stop bits) from the received asynchronous signal and storing the actual data bits in a register to await transmission to the synchronous system. The data is read from the register at the rate required by the synchronous system. At the same time, the information required by the transmission format of the synchronous system, such as synchronization and control information, is combined with it. Such a solution is disclosed, for example, in U.S. Patent 5,054,020.

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However, prior art solutions are quite complex and require, for example, a large register and a lot of different logic, in which case they also require space on a circuit board or microcircuit.

The object of the present invention is to overcome the drawbacks described above and to provide a solution which enables a very simple practical implementation. This object is achieved by a method and an apparatus according to the invention, the method being characterized by what is described in the characterizing part of the appended claim 1 and for the device by what is described in the characterizing part of the appended claim 4.

The idea of the invention is to implement rate equalization between the incoming and outgoing signal by implementing a controlled overflow or underflow of the asynchronous signal termination! at the start bit. Thanks to the solution, only a one-bit register can be used for buffering.

The signal transmitted to the synchronous system must also be able to be transmitted back to the asynchronous device. This transfer is effected by adding, in the absence of a start or stop bit from the signal of the signal to be transmitted back (Dss) to the corresponding signal of the output signal (Da>), the following characters are abbreviated according to the start or stop bit, so that the combined effect of the reductions compensates. addition.

In the following, the invention and its preferred embodiments will be described in more detail with reference to the examples according to the accompanying drawings, in which Fig. 1 shows a block diagram of a device according to the invention implementing asynchronous signal transmission to a synchronous system, Fig. 2 shows transmission according to Fig. 1 as a signal diagram. synchronized

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3 93290 is slower than the incoming asynchronous signal rate, Fig. 3 shows the transmission by the device of Fig. 1 as a signal diagram in the case where the data transmission to the synchronous system is faster than the incoming asynchronous signal rate, Fig. 4 is a block diagram of the device transmitting to the synchronous system transfer back to the asynchronous device, and Fig. 5 shows the transfer performed by the device of Fig. 4 as a signal diagram.

Figure 1 shows a device according to the invention which converts an asynchronous signal Da from an asynchronous device AD, e.g. a modem, into a synchronous signal Dss transmitted to a synchronous system SS. First, the device comprises first and second frequency dividers 11 and 12, respectively, to which a clock signal C1 having a higher frequency, obtained from a synchronous system SS, is fed. This clock may be a direct system clock of the synchronous system 20 or may be derived from an oscillator locked to the master clock of the synchronous system. The first frequency divider can thus also be located in a synchronous system. The asynchronous signal Da is connected to the data input 25 of the data-25 of the one-bit register 15. and directs write to register 16 (i.e., read from register 15) to register 16 on the synchronous system side. The data displayed at the output of the register 15 forms a signal Ds, which is further transmitted to the synchronous system SS so that the synchronous system 35 takes samples in question. signal 4 93290 (reading signal) at regular intervals. For this purpose, the signal Ds is connected on the synchronous system side to the data input D of the one-bit register 16. A read from the register 15 (i.e. a write to the register 16) takes place on the rising edge of the clock Cn. The asynchronous signal Da is further connected to an edge detection circuit 13 which detects the rising (or alternatively falling) edges of the asynchronous signal by means of a higher frequency clock C1 connected to the circuit 13. The output of the edge detection circuit 13 is connected to the first input of the centering logic circuit 14. The centering logic circuit counts (in addition to also centering the sample clock Cs as described later) the bits of each character (the sequence number of bits within each character). A clock signal Cs acting as a sampling clock is in turn connected to the second input of the central logic circuit 14, and the output of the circuit is connected to control a second frequency divider 12.

The operation of the device will now be described in more detail with reference to Fig. 2, which shows a read clock Cn, a write clock Cs, and signals Da and Dss. In this case, one character of the incoming asynchronous signal Da consists of eight consecutive bits, the first of which is always the start bit B and the last the end bit E. Between the start and end bits are the bits constituting the actual payload data, in this case numbered sequentially from 1 to 24. The signal Dss is shown below the asynchronous signal Da. It should therefore be noted that the the sig-30 nals are divided into two different rows in the figure. The same is true for the sampling clock Cs shown above the asynchronous signal Da.

The incoming data Da are sampled in the register 15 on the rising edge of the sampling clock Cs and the samples 35 are read from the register (written to the register 16) at the clock li 5 93290

Cn on the rising edge. For example, the first start bit B is thus written to register 15 at time T1 and read from register at time T2. The edge detection circuit 13 constantly monitors the edge points of the signal Da, and the centering-5 logic circuit counts from the sequence number of bits within the character. Sampling is started in the middle of the start bit, but since the speed of the incoming signal Da differs slightly from the sampling frequency, the sampling moment gradually slides towards the edge of the bit. When it comes to the end bit E of the first character 10, it is written to register 15 at time T8. Thereafter, since the centering logic circuit 14 has detected that the number of bits per character is full, it accepts the next edge between the end and start polarities. With this edge, the centering logic circuit 15 centers the sample clock Cs so that its rising edge comes again in the middle of the start bit B. Thus, at this stage, the phase between the clocks Cn and Cs is slid (the sliding resolution depends on the resolution of the edge detection), whereby the rising edge of the sample clock Cs moves in front of the corresponding rising edge of the reading clock Cn. As a result, the next start bit B of the signal Da is written to the register 15 before the previous end bit is read from there. Thus, at this point, a controlled overflow according to the invention, i.e. the termination bit, takes place in a controlled manner from the signal Dss.

After this, the operation continues in the same way, i.e. after the end bit of each character, the sample clock Cs is centered so that its rising edge comes again in the middle of the start bit 30B. The termination bit disappears again when the sliding of the clock Cs moves its leading edge to the other side of the leading edge of the clock Cn so that there are two leading edges of the clock Cs between the two leading edges of the clock Cn.

Figure 2 showed a case where the transmission to the synchronous system is slower than the rate Da of the incoming asynchronous signal. Figure 3 shows the opposite case, i.e. the case where the sampling moment gradually slides towards the leading edge of the bit.

In this case, too, sampling is started in the middle of the start-5 bit. When it comes to the end bit E of the first character, it is written to the register at time T8. Thereafter, since the number of bits per character is full, the centering logic circuit 14 accepts the next edge between the end and start polarities. With this edge 10, the centering logic circuit re-centers the sample clock Cs so that its rising edge re-enters the center of the start bit B. Thus, at this stage, the mutual phase of the clocks Cn and Cs is slid so that the rising edge of the sample clock Cs moves behind the rising edge 15 of the reading clock Cn. As a result, the end bit is read from register 15 twice before the next start bit is written to the register. Thus, at this point, a controlled under-leakage according to the invention takes place, i.e. the termination bit is duplicated in a controlled manner to the signal 20 Dss.

After this, the operation continues in the same way, i.e. after the end bit of each character, the sample clock Cs is centered so that its rising edge comes again in the middle of the start bit B. The end bit is doubled again when the sliding of the clock Cs 25 moves its leading edge to the other side of the leading edge of the clock Cn so that there are two leading edges of the clock Cn between the two leading edges of the clock Cs.

The solution according to the invention for transferring an asynchronous signal to a synchronous system has been described above. The number of stop bits in the characters of the synchronous signal Dss depends on how many stop bits are in the characters of the signal from the asynchronous device. In general, however, it can be seen that if the method according to the invention changes the number of stop bits in a character, it occurs either by increasing the number of stop bits in that character by one.

However, the synchronous signal Dss obtained by the method described above must be able to be transmitted in another transmission direction, i.e. back to the asynchronous device, in which case it is necessary to take into account e.g. the fact that the signal sent to the asynchronous device must always include a stop bit (one or more). Figure 4 shows a device which transfers the signal transmitted to the synchronous system SS back to the asynchronous device AD using the method according to the invention. Again, the device comprises a one-bit register 45 from which the asynchronous signal Da is read to the asynchronous device AD. In addition, the device comprises a frequency divider 15, a phase counter 42, a control and signal logic circuit 43, a TA1 port 44 and a comparator 46. The clock signal C1, again obtained from the synchronous system SS, is connected to the frequency divider input, phase counter 42 clock input C, control and logic circuit 43 clock-20 to weather input C and register 45 to clock input C. The output of the frequency divider 41 is connected to the first input of the comparator 46 and the output of the phase counter 42 to its second input. The output of the phase counter is further connected to one of the inputs 25 of the control and logic circuit 43, so that the control and logic circuit also receives information about the respective phase of the phase counter. The output of the comparator is connected to the Enable input E of the register to allow writing to the register. The signal Dss from the synchronous system is connected to the second input 30 of the OR gate 44 and to the input EP of the control and logic circuit. An OR gate, the output of which is connected to the data input D of the register 45, is used to force a stop bit on the signal to be written to the register even when it is missing from the incoming signal Dss. Through its Si-35 weather input EP, the control and logic circuit 43 monitors the termination polarities of the signal Dss (polarity at the assumed termination bit). In order for the control and logic circuit 43 to control the stepping of the phase counter, the first output of the control and logic circuit 43 is connected to the Enable input E of the 5 phase counter.

The operation of the device will now be described in more detail with reference to Fig. 5. The reference numeral Dss denotes the signal from the synchronous system SS, which is written to the register 45, and the reference symbol Da denotes the signal transmitted from the synchronous system to the asynchronous device AD. These signals are shown in Fig. 5 in a manner similar to Figs. 2 and 3 above, i.e., by denoting the start bit of each character by reference character B and the end bit by reference character E, and by numbering the payload bits sequentially (numbering from 1 to 36). The signal Dss in this case is as shown in Fig. 2, i.e. such that its first character lacks a stop-20 bit E. Fig. 5 further shows the phase Dss of the incoming data with four different vertical lines a, b, c and d, which illustrate the possible (clock signal Cn phase-bound) sampling times at which the value of the incoming signal Dss can be written to register 45. The lines indicated by the sign Vii-25 Φ describe the respective phase of the phase counter 42 by a line corresponding to one of the lines ad, i.e. one of the four phases of the incoming data.

From the start bit B of the signal Dss to the last useful bit 6 of the first character, the following occurs. When the phase of the clock signal Cn from the frequency divider 41 (represented in this case by two bits) matches the reading of the phase counter 42 (also represented by two bits), the comparator allows the value of the signal Dss to be written to the register by applying a write enable signal to the buffer input 35. In Fig. 5, these sampling moments li 9 93290 are shown as moments when the line (a-d) describing the phase of the phase counter intersects with the corresponding vertical line (a-d). The corresponding bit appears immediately at the output of register 45, so that the leading edge of the Da bit of the signal hits those 5 intersections. The control and logic circuit counts the written bits from the interface between the end and start bits found. When it comes to the end bit E, the control logic 43 forces the end polarity 10 to be written to the register by means of the OR gate 44 (usually a logic value of one is used as the end polarity). At the same time, the control and logic circuit 43 checks (via its input EP) whether the incoming data Dss actually had a termination polarity at its assumed location. If it was not (as is the case in the example in the figure), the control and logic circuit 15 (by applying an enable pulse to the input of the phase counter E) allows the phase counter 42 to be stepped to the next step, indicated by line d in the figure. As a result, a 3/4 bit stop bit is added to the outgoing signal in place of the missing 20 stop bits and samples are started shifted. The magnitude of the transfer in this case is 25% of the length of one bit. In this way, it is continued again until the next termination polarity, at which point the phase counter is stepped again at the termination bit (point P1). In this case, the stop bit this time in the incoming signal (the stop bit after bit 12) is shortened (25%) because the next sample is taken correspondingly earlier. The control and logic circuit allows the phase counter to be incremented only at the end bit, and even then only if the signal Dss in the phase counter 30 rest phase (line a) has no end polarity or if the phase counter phase is other than the rest phase (lines b, c and d). Thus, when the phase counter has stepped back to its rest phase (solid line a) at the end bit after bit 24, it remains there until the end bit is again missing from its assumed position.

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As described above, the addition of a 3/4 bit length stop bit after bit 6 is compensated by shortening the three end bits by a quarter. The added end bit and the abbreviated end bits are shown in italics in Figure 5-5. Thus, the signals Da of the signal going to the asynchronous device always also have a stop bit. If the end bit is missing from the incoming signal Dss, it is incremented by the amount T / n abbreviated (T is the length of the bit), and the end bits following n-1 are shortened accordingly 10 so that the increment performed is compensated. Although an example has been given above in which the stop bit is shortened by 25%, the shortening can also be smaller, e.g. 12.5%, in which case a signal bit with a length of 7/8 of the nominal length is given to the signal Da.

Note that the operation of the example above requires that the incoming signal does not have a missing stop bit for a time interval of the next three characters after the character that is missing the stop bit. If the bit shortening is less than a quarter, the time interval of 20 is correspondingly longer.

If there are two consecutive termination bits in the sign of the signal Dss, as in the example shown in Fig. 3, they are allowed to pass as such to the asynchronous device. However, if the signal Dss has two or more consecutive stop bits before the added stop bit is compensated, the phase counter is reset directly to the rest phase at the additional stop bit.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified within the scope of the inventive idea set forth above and in the appended claims. Although the formation of an underflow or overflow and the addition of a shortened bit have been described above specifically at the end bit, the idea of the invention can be applied instead of the end bit.

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11 93290 equally well for the start bit, which is why the start and end bits are also presented as alternatives in the claims.

Although the requirements speak of a register of one bit in length, it is of course possible to use longer 5 memory spaces or to store different bits in different memory locations. However, it is essential for the invention that the data to be stored in the memory at a time takes up only one bit of memory. Thus, when we speak of a one-bit register in this context, it must be understood as the memory space required for the data to be stored 10 at a time.

Such a memory space can be, for example, a D-type flip-flop. Although the devices for the different transmission directions have been shown above (for the sake of clarity) as completely separate, the same components can, of course, be used in both devices.

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Claims (5)

A method for transmitting an asynchronous signal (Da) to a synchronous system (SS), according to which a speed equalization between the incoming signal (Da) and the output signal (Ds), characterized by that the speed equalization is carried out by means of a register (15) of a bit length, such that it is entered and read from the register mainly in turns, and that at the start or end bit (B or E) of the signal, wasting or bottling of the register is caused by change of the reading and writing order. 2. A method according to claim 1, characterized in that spills or bottoms are caused at the end bit (E) of the signal. 3. A method according to claim 1, characterized in that the reading and writing order is changed by shifting the phase of the clock signal (Cs) which handles the entry in the register (15) relative to the phase of the clock signal (Cn). who performs the reading from the register says that the mutual order of their reading and writing flanks is changing. Device for transmitting an asynchronous signal (Da) to a synchronous system (SS), comprising: - a register (15) in which incoming data is entered and from which output data is read, and - detector means (13) for detection the flanks of the incoming asynchronous signal, characterized in that the register consists of a bit-long memory element (15), and that the device further comprises means (14) coupled to the detector means for changing the mutual order of said read and write events in response to observation of occurrence of start and / or end polarity in the asynchronous signal. 93290 Device according to claim 4, characterized in that said means for changing the mutual order of the read and write events comprises means (14) for shifting the write clock (Cs) 5 phase in relation to the the register reading clock (Cn).