AU6378194A - Method and device for transmitting an asynchronous signal toa synchronous system - Google Patents

Description

Method and device for transmitting an asynchronous signal to a synchronous system

The invention relates to a method for trans- mitting an asynchronous signal to , a synchronous system, wherein matching of speeds is performed be¬ tween the inbound signal and an outbound signal, and to a device for transmitting an asynchronous signal to a synchronous system, comprising a register into which inbound data is written and from which data is read forward, and identification means for identifying the edges of the inbound asynchronous signal.

The solution according to the invention allows asynchronous devices to be connected to synchronous devices or synchronous transmission systems. Such asynchronous devices include e.g. modems, computers, computer terminals, various measuring devices and printers. In particular, it is known to employ modems in communication over telephone lines between com- puters. At the transmission end a modem modulates the carrier and transmits the modulated signal to the telephone line. At the reception end, another modem demodulates the received signal into the original data signal in order that the recipient computer would be able to process the data. Between the transmission and reception ends the asynchronous signal transmitted by the modem has been transmitted in a synchronous trans¬ mission system, such as a PCM system. The synchronous device or transmission system refers to a device or system in which transmission takes place synchron¬ ously, i.e. such that there are always an integer number of time slot units between two significant time instants of the signal.

In the prior art solutions, start bits and stop bits are usually first removed from an asynchronous signal to be received whereas the actual data bits are stored in a register where they wait for transmission to the synchronous system. Data is read from the re¬ gister at a speed required by the synchronous system. At the same time, data required by the transmission format of the synchronous system, such as synchron¬ ization and control data, are inserted in the data. This kind of solution is disclosed e.g. in US Patent 5,054,020. The prior art solutions, however, are relatively complicated and require e.g. a large register and a wide variety of logic means, thus also requiring plenty of space on the printed circuit board or micro- circuit. The object of the present invention is to avoid the above-described drawbacks and provide a solution which allows a very simple practical implementation. This object is achieved by a method and a device according to the invention. The method according to the invention is characterized in that the matching of speeds is performed by a register one bit in length such that as a general rule writing into and reading from the register take place alternately while a register overflow or underflow is effected at a signal stop bit or start bit by changing the reading and writing order. The device in turn is characterized in that the register comprises a memory space one bit in length, and that the device further comprises means connected to the identification means for altering the mutual order of the reading and writing processes in response to the detection of the presence of a start and/or stop polarity in the asynchronous signal.

The invention is based on the idea that the matching of speeds between an inbound and outbound signal is performed by a controlled overflow or under- flow at the stop or start bit of the asynchronous signal.

It is also necessary that the signal transmitted to a synchronous system can be transmitted back to an asynchronous device. To achieve this,_% when the start bit or stop bit is missing from the character of the signal to be transmitted back, the concerned bit is inserted in the corresponding character of the out¬ bound signal in shortened form, and the start or stop bit is shortened in the next n characters so that the combined effect of the shortenings made compensates for said insertion.

In the following the invention and its preferred embodiments will be described more fully with refer- ence to the examples of the attached drawings, in which

Figure 1 is a block diagram illustrating a device according to the invention which realizes the transmission of an asynchronous signal to a synchron- ous system;

Figure 2 is a signal diagram illustrating trans¬ mission realized by the device shown in Figure 1, where data transmission to the synchronous system takes place at a speed lower than that of the inbound asynchronous signal;

Figure 3 is a signal diagram illustrating trans¬ mission realized by the device shown in Figure 1, where data transmission to the synchronous system takes place at a speed higher than that of the inbound asynchronous signal;

Figure 4 is a block diagram illustrating a device which realizes the transmission of a signal transmitted to a synchronous system back to an asyn¬ chronous device; and Figure 5 is a signal diagram illustrating the transmission realized by the device shown in Figure 4. Figure 1 shows a device according to the inven¬ tion which converts an asynchronous signal Da from an asynchronous device AD, such as a modem, into a syn- chronous signal Dss transmitted to_% a synchronous system SS. The device comprises a first and a second frequency divider 11 and 12, respectively, to which a higher-frequency clock signal Cl from the synchronous system SS is applied. This clock may be directly the system clock of the synchronous system, or it may be derived from an oscillator locked to the master clock of the synchronous system. The first frequency divider may thus be positioned in the synchronous system as well. The asynchronous signal Da is connected to a data input D in a register 15 one bit in length. Asynchronous data is written into the register 15 in synchronization with a clock signal Cs derived from the second frequency divider 12. The clock signal Cs is connected to a clock input C in the register 15. A clock signal Cn from the first frequency divider 11 is applied to the side of the synchronous system, and it is employed to control writing into a register 16 on the side of the synchronous system (i.e. reading from the register 15). Data at the output of the register 15 forms a signal Ds, which is forwarded to the syn¬ chronous system SS such that the synchronous system samples the signal (reads the signal) at regular intervals. To this end, the signal Ds is connected to a data input D in the register 16 one bit in length on the side of the synchronous system. Reading from the register 15 (i.e. writing into the register 16) takes place by the rising edge of the clock Cn. The asyn¬ chronous signal Da is also connected to an edge identification circuit 13 which identifies the rising (or falling) edges of the asynchronous signal by utilizing the higher-frequency clock Cl, which is connected to the circuit 13. The output of the edge identification circuit 13 is connected to a first input in a centering logic circuit 14. The centering logic circuit counts (in addition to centering the sample clock Cs in a manner to be described below) bits in each character (consecutive bits within each character). The clock signal Cs serving as a sampling clock is in turn connected to a second input (clock input) in the centering logic circuit 14, and the output of the circuit is connected to control the second frequency divider 12.

The operation of the device will be described in greater detail below with reference to Figure 2, which shows the read clock Cn, the write clock Cs and the signals Da and Dss. In this specific case, one char¬ acter of the inbound asynchronous signal Da consists of eight consecutive bits, of which the first is always a start bit B and the last is a stop bit E. Payload data bits between the start bit and the stop bit are herein indicated by consecutive numbers from 1 to 24. The signal Dss is shown below the asynchronous signal Da. It is thus to be noted that these signals are divided on two different rows in the figure. The same applies to the sampling clock Cs, which is shown above the asynchronous signal Da.

The inbound data Da is sampled into the register 15 by the rising edge of the sampling clock Cs, and the samples are read from the register (written into the register 16) by the rising edge of the clock Cn. For instance, the first start bit B is written into the register 15 at a time Tl, and it is read from the register at a time T2. The edge identification circuit 14 monitors the edge areas of the signal Da continu- ously, and the centering logic circuit counts the consecutive bits within the character. Sampling is started in the middle of the start bit, but as the speed of the inbound signal Da deviates somewhat from the sampling frequency, the sampling time slides gradually towards the edge of the bit._% On reaching the stop bit E of the first character, the stop bit is written into the register 15 at a time T8. Thereafter, as the centering logic circuit 14 has detected that the number of bits per character is full, it accepts the following edge between the stop and start polar¬ ities. The centering logic circuit centers the sampling clock Cs by using this edge so that the rising edge of the clock Cs will again be positioned in the middle of the start bit B. At this stage the mutual phase of the clocks Cn and Cs is allowed to slide (the sliding resolution depends on the resolution of the edge identification), so that the rising edge of the sampling clock Cs shifts in this specific case in front of the corresponding rising edge of the read clock Cn. As a result the next start bit B of the signal Da is written into the register 15 before the preceding stop bit is read from it. The controlled overflow according to the invention thus takes place at this stage, i.e., the stop bit is deleted from the signal Dss in a controlled manner.

Thereafter the operation continues in the same way, i.e. the sampling clock Cs is centers after the stop bit of each character so that the rising edge of the sampling clock will again be positioned in the middle of the start bit B. The stop bit again dis¬ appears when the sliding of the clock Cs shifts its leading edge so that it occurs earlier than the corresponding leading edge of the clock Cn, and so there are two leading edges of the clock Cs between two consecutive leading edges of the clock Cn. In the case shown in Figure 2, transmission to the synchronous system takes place at a speed lower than that of the inbound asynchronous signal Da. Figure 3 shows the reverse case, in which the sampling time slides gradually towards the leading edge of the bit.

Even in this case the sampling is started from the middle of the start bit. On reaching the stop bit E of the first character, the stop bit is written into the register at a time T8. Thereafter, as the number of bits per character is full, the centering logic circuit 14 accepts the next edge between the stop and start polarities. The centering logic circuit again centers the sampling clock Cs by this edge so that the rising edge of the sampling clock will again be posi¬ tioned in the middle of the start bit B. At this stage, the mutual phase of the clocks Cn and Cs is allowed to slide so that the rising edge of the sampl¬ ing clock Cs occurs later than the rising edge of the read clock Cn. As a result, the stop bit can be read twice from the register 15 before the next start bit is written into the register. The controlled underflow according to the invention thus takes place at this stage, i.e. the stop bit is duplicated in the signal Dss in a controlled manner.

Thereafter the operation continues in the same way, that is, the sampling clock Cs is centered after the stop bit of each character so that the rising edge of the sampling clock will again be positioned in the middle of the start bit B. The stop bit is again duplicated when the sliding of the clock Cs shifts its leading edge so that it occurs later than the corre¬ sponding leading edge of the clock Cn, and so there are two leading edges of the clock Cn between two consecutive leading edges of the clock Cs. The edge identification circuit 13 is implement¬ ed by sampling the inbound signal. Sampling may take place e.g. by using flip-flops. The centering logic circuit 14 may contain e.g. a counter which monitors the character length by counting clock pulses Cs. When the full character length is reached, the counter stops until the first edge identification pulse is received from the edge identification circuit 13, at which stage the counter is restarted, and the center- ing logic circuit applies a control pulse to the frequency divider 12, which control pulse charges the frequency divider with a predetermined value centering the clock in an appropriate position.

A solution according to the invention for trans- mitting an asynchronous signal to a synchronous system has been described above. The number of stop bits within the characters of the synchronous signal Dss depends on how many stop bits there are in the char¬ acters of the signal from the asynchronous device. Generally speaking, it can be stated, however, that if the method according to the invention changes the number of stop bits within the character, this takes place either such that the number of stop bits in the particular character increases or decreases by one. However, it is also necessary that the syn¬ chronous signal Dss achieved by the method according to the invention can also be transmitted in the reverse transmission direction, i.e. back to the asynchronous device. It is thereby to be noted, among other things, that there always has to be a stop bit (at least one) within each character of the signal to be transmitted to the asynchronous device. Figure 4 shows a device which transmits a signal transmitted to a synchronous system SS by the method according to the invention back to an asynchronous device AD. Also in this case the device comprises a register 45 one bit in length, from which an asynchronous signal Da is read to an asynchronous device AD. The device further comprises a frequency divider 41, a phase counter 42, a control and character logic circuit, 43, an OR gate 44, and a comparator 46. A clock signal Cl, which is again obtained from the synchronous system SS, is connected to an input in the frequency divider, to a clock input C in the phase counter 42, to a clock input C in the control and logic circuit 43, and to a clock input C in the register 45. The output of the frequency divider 41 is connected to a first input in a comparator 46, and the output of the phase counter 42 in turn is connected to a second input in the comparator. The output of the phase counter is also connected to one input in the control and logic cir¬ cuit 43, in order that the control and logic circuit would also be informed of the current phase of the phase counter. The output of the comparator is con- nected to an Enable input E in the register to allow writing into the register. A signal Dss from the synchronous system is connected to one input in the OR gate 44 and to an input EP in the control and logic circuit. The OR gate having its output connected to a data input D in the register 45 forces a stop bit to be inserted into the signal to be written into the register even in cases where there is no such bit in the inbound signal Dss. Through its input EP the control and logic circuit 43 monitors the stop polar- ities of the signal Dss (polarity at the assumed stop bit). In order that the control and logic circuit 43 could control the stepping of the phase counter, the first output of the control and logic circuit 43 is connected to the Enable input E of the phase counter. The second output of the control and logic circuit is connected to the OR gate 44 for the above-mentioned forced insertion of the stop polarity.

The operation of the device will now be de¬ scribed more closely referring to Figure 5. The refer- ence Dss indicates a signal from the synchronous system SS, which signal is to be written into the register 45, and the reference Da indicates a signal which is transmitted from the synchronous system to the asynchronous device AD. These signals are shown in Figure 5 in a similar way as in Figures 2 and 3, i.e. the start bit of each character is indicated with B and the stop bit with E, while payload bits are given consecutive numbers (1 to 36). In this case, the signal Dss is such as shown in Figure 2, i.e. there is no stop bit E in its first character. Further in Figure 5, the phase of the inbound data Dss is indicated by four vertical lines a, b, c and d, which represent possible sampling times (which are bound to the phase of the clock signal Cn) at which the value of the inbound signal Dss can be written into the register 45. The rows indicated with the reference represent the current phase of the phase counter 42 by a line which corresponds to one of the lines a to d, i.e. one of the four phases of the inbound data. The steps from the start bit B of the signal Dss to the last payload bit 6 of the first character are as follows. When the phase of the clock signal Cn from the frequency divider 41 (the phase is here represent¬ ed by two bits) matches with the reading of the phase counter 42 (the reading is also represented by two bits), the comparator allows the value of the signal Dss to be written into the register by applying a writing enabling signal to the input E(nable) of the buffer. In Figure 5, the sampling times are shown as time instants when the line (a to d) standing for the phase of the phase counter intersects a corresponding vertical line (a to d). The respective bit appears immediately at the output of the register 45, so that the leading edge of the bit of the signal Da hits the intersection points. The control and logic circuit counts the bits that have been written, beginning from the detected boundary between the stop and start bits. On reaching the stop bit E, the control logic 43 forces the OR gate 44 to cause the stop polarity to be written into the register (the stop polarity is usually the logic value one). At the same time the control and logic circuit 43 checks (through its input EP) whether the inbound data Dss really contains the stop polarity in its assumed position. If there is no stop polarity (as in the example shown in the figure), the control and logic circuit allows (by applying an enabling impulse to the input E of the phase counter) the phase counter 42 to take a step to the following phase, indicated by the line d in the figure. As a result, a stop bit having the length of a 3/4 bit is inserted in the outbound signal at the position of the missing stop bit, and the sampling is continued with a phase shift. In this case, the magnitude of the shift is 25% of the length of one bit. This is continued up to the next stop polarity, whereat the phase counter again takes a step (point PI) at the stop bit. The stop bit in the inbound signal (the stop bit after the bit 12) is now shortened by 25% as the following sample will be taken correspondingly earlier. The control and logic circuit allows the phase counter to take a step only at the stop bit and even then only if the signal Dss received during the rest phase of the phase counter (line a) does not contain any stop polarity or if the phase counter is not in the rest phase but in some other phase (lines b, c and d). In other words, after the phase counter has stepped back to its rest phase (continuous line a) at the stop bit positioned after the bit 24, it will remain there until the stop bit is again missing from its assumed position.

In the above-described way, the insertion of the stop bit having the length of a 3/4 bit after the bit 6 is compensated for by shortening three stop bits each by one quarter. In the figures, the inserted stop bit and the shortened stop bits are shown as hatched areas. The characters of the signal Da applied to the asynchronous device thus always include a stop bit. If the stop bit is missing from the inbound signal Dss, it is inserted shortened by an amount T/n (where T stands for the bit length), and n-1 following stop bits are shortened correspondingly so that the per¬ formed insertion will be compensated for. Even though the stop bit is shortened by 25% in the above example, the shortening may be smaller as well, e.g. 12.5%, in which case a stop bit having a length 7/8 of its nominal length is inserted into the signal Da.

It is to be noted that an operational require¬ ment of the above example is that after the character from which the stop bit is missing the missing stop bit does not occur in the inbound signal for a time period corresponding to the three next characters. If the shortening of the bits is less than one quarter, the time period is correspondingly longer.

If, as shown in the example of Figure 3, the character of the signal Dss has two consecutive stop bits, they are allowed to pass through to the asyn¬ chronous device as such. However, if the signal Dss comprises two or more consecutive stop bits before the compensation of the inserted stop bit, the phase counter is directly set to the rest phase at the extra stop bit.

Even though the invention has been described above with reference to the examples of the attached drawings, it is self-evident that the invention is not restricted to them but it may be modified within the inventive idea disclosed in the text above and in the attached claims. Even though the establishment of underflow and overflow and the insertion of a shorten¬ ed bit have been described above referring to the stop bit, the idea according to the invention is equally applicable to the start bit, wherefore the start bit and stop bit are set forth as alternatives even in the claims. Even though the claims refer to a register one bit in length, it is, of course, possible to use a longer memory space, or different bits can be stored in different memory positions. However, in view of the invention, it is essential that the data to be stored in the memory at one time takes only a single-bit memory position. When a register one bit in length is referred to in this text, it is to be understood as a memory space required by data to be stored at one time. The memory space may be e.g. a D-type flip-flop. Even though the equipment in the different trans¬ mission directions are shown above apart from each other (for the sake of clarity), the same components can, of course, be used in both equipment.

Claims (5)

Claims:

1. Method for transmitting an asynchronous signal (Da) to a synchronous system (SS), wherein matching of speeds is performed between the inbound signal (Da) and an outbound signal (Ds), c h a r¬ a c t e r i z e d in that the matching of speeds is performed by a register (15) one bit in length such that as a general rule writing into and reading from the register take place alternately while a register overflow or underflow is effected at a signal stop bit or start bit (B or E) by changing the reading and writing order.

2. Method according to claim 1, c h a r a c- t e r i z e d in that the overflow or underflow is effected at the signal stop bit (E).

3. Method according to claim 1, c h a r a c¬ t e r i z e d in that the reading and writing order is altered by sliding the phase of a clock signal (Cs) taking care of writing into the register (15) with respect to the phase of a clock signal (Cn) taking care of reading from the register such that the mutual order between the read and write edges of the clock signals changes.

4. Device for transmitting an asynchronous signal (Da) to a synchronous system (SS), comprising

- a register (15) into which inbound data is written and from which data is read forward, and

- identification means (13) for identifying the edges of the inbound asynchronous signal, c h a r¬ a c t e r i z e d in that the register comprises a memory space (15) one bit in length, and that the device further comprises means (14) connected to the identification means for altering the mutual order of the reading and writing processes in response to the detection of the presence of a start and/or stop polarity in the asynchronous signal.

5. Device according to claim 4, c h a r a c t e r i z e d in that said means for altering the mutual order of the reading and writing processes comprise means (14) for sliding the phase of a write clock (Cs) for the register (15) with respect to a read clock (Cn) for the register.