JPH0666749B2 - Branch circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch circuit, and more particularly, to a high-speed digital digital relay transmission system in which a low-speed signal added to a high-speed digital signal by a terminal repeater together with a synchronization signal. O / H (overhead) for meeting signals, fault information signals, etc.
The present invention relates to a branch circuit for detecting and separating a bit signal in an intermediate relay station.

2. Description of the Related Art FIG. 2 shows a signal frame configuration example, and FIG. 3 shows a conventional circuit configuration example.

The digital relay signal including the O / H bit input to the input terminal DATA IN is sequentially held in the shift register composed of flip-flops F / F 1 to F / FN by the input clock CLK. Flip Flop F / F 1 to F / F
The output of each stage of the shift register constituted by N is connected to the synchronization detecting circuit 11, and the output Q is connected from the output flip-flop F / F 1'to the data input terminal D of F / FN '. .

After confirming frame synchronization Shift register (F / F 1 to F / F
Only the O / H bit in the digital relay signal held in N) is sent from the flip-flop F / F 1 ′ for output to the output terminal of F / FN ′ by the timing signal supplied from the timing circuit 12.

Problems to be Solved by the Invention However, the above-mentioned configuration has a drawback that the number of output flip-flops is large and power consumption is increased.

The present invention has been made to solve the above-mentioned drawbacks inherent in the prior art. Therefore, the object of the present invention is to divide an O / H bit added together with a synchronizing signal into a digital relay signal. , It is to provide a novel branch circuit capable of reducing power consumption by reducing the number of output gates as much as possible.

Means for Solving the Problems In order to achieve the above object, the branch circuit according to the present invention is
/ H bit and a frame shift bit for branching the O / H bit are alternately added to the higher order group digital signal as a shift register, and a clock frequency of the input digital relay signal and the clock frequency. A low-speed timing signal is input and the clock frequency is output as the clock of the shift register before the frame sync signal is detected, and the frame sync signal is detected by holding the O / H data in the shift register and then the next frame sync signal. And a clock selection circuit that outputs the low-speed timing signal as a clock of the shift register until the detection of (1), the O / H bit is sent to the shift register output by the low-speed timing signal. To do.

BEST MODE FOR CARRYING OUT THE INVENTION Next, the present invention will be specifically described with reference to the drawings with respect to a preferred embodiment thereof.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The digital relay signal having the frame structure as shown in FIG. 2 including the O / H bit signal and the frame synchronizing signal is sequentially flip-flop F / F 1 to F / F by the input clock.
It is held in a shift register composed of N. The output of each stage of the shift register is connected to the synchronization detection circuit 11 and the frame synchronization signal is detected.

After the frame sync signal is detected, after the O / H bit information is held in the shift register, the clock supplied to the shift register is supplied from the timing circuit 12 by the selection circuit 14 composed of a gate. Switching to the speed clock, the O / H bit information is sent to the DATA output terminal before the next frame sync bit is input to the data terminal D of the flip-flop F / F 1.

A timing chart of the above operation is shown in FIG.

After sending the O / H bit to the DATA output, the signal applied to the clock input of the flip-flop of each shift register is switched again to the clock of the digital relay signal to confirm the frame sync signal.

According to the circuit configuration of the present invention, it is possible to reduce the number of output gates when the O / H bit in the digital relay signal is branched, and the circuit of relatively low power consumption is provided. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing an example of a frame structure of a signal, FIG. 3 is a block diagram of a conventional circuit of this type, and FIG. 4 is a timing chart showing the operation of the present invention. F / F 1 to F / FN, F / F 1'to F / FN '... flip-flop, 11 ... synchronization detection circuit, 12 ... timing circuit,
13 …… Synchronous protection circuit, 14 …… Selection circuit

Claims (1)

[Claims] 1. A shift register which receives a digital relay signal in which an O / H bit and a frame synchronization bit for branching the O / H bit are alternately added to a high-order group digital signal, and a clock of the input digital relay signal. Frequency and a timing signal lower than the clock frequency are input, the clock frequency is output as the clock of the shift register before the detection of the frame synchronization signal, and the O / H data is detected after the detection of the frame synchronization signal. And a clock selection circuit that outputs the low-speed timing signal as a clock of the shift register until the next frame synchronization signal is detected after being held at
A branch circuit characterized by sending O / H bits to a shift register output by a low-speed timing signal.