FI79637C - KRETSKOPPLING FOER EN FASLAOST SLINGA. - Google Patents

Description

1 79637

Phase locked loop connection

The present invention relates to a phase-locked loop circuit comprising, in series, a digital phase comparator having a reference frequency applied to its second input, a loop filter and a voltage controlled oscillator from which a feedback branch is derived to the second input of the phase comparator.

Such a phase-locked loop is shown as a block diagram in Figure 1. It introduces a reference frequency fref to the input of the phase comparator 1. The output of the phase comparator is connected to a loop filter 2 and its output is further connected to a voltage controlled oscillator 3. The output of the oscillator 3 is connected back to the phase comparator 1 so that a loop is obtained at a certain speed according to the reference frequency fref.

It is well known to use such a phase-locked loop in e.g. frequency synthesizers. When a phase-locked loop is used in frequency synthesis, the voltage-controlled oscillator (VCO) of which is frequency modulated, conflicting requirements for the loop speed arise. If a fast settling time is desired when switching from one channel to another, the cut-off frequency of the loop must be as high as possible. On the other hand, so that the loop does not emphasize or attenuate the modulation, the cut-off frequency of the loop should again be small, more specifically, the cut-off frequency should be much lower than the lowest modulation frequency. In addition, the low cut-off frequency has the advantage that the residual modulation is reduced and a higher attenuation is obtained for the phase reference frequency.

For example, it is known from U.S. Patents 4,482,869 and 4,516,083 and from EP Patent Application 85615 to speed up a fluff filter by changing the resistance value of the integrator stage of the filter by either removing or shorting the resistors. Equivalent to 2,79637, the deceleration is based on removing short circuits or adding resistors. U.S. Patent 4,156,855 further accelerates the loop by increasing the current supplied to the capacitor of the integrator stage by means of a current pump.

However, controlling the resistors with switches interferes with the operation of the loop. For example, at the time of switching on a slow loop, there is usually a momentary jerk in the control voltage of the VCO from the filter, which cannot be allowed, for example, in radiotelephone applications. The same happens if the current charging the integrator suddenly changes.

Thus, without interference, it has not been possible to use frequency synthesis formed by phase-locked loop when, on the one hand, a fast settling time and, on the other hand, a linear modulation frequency response are required. When modulated frequency synthesis formed by a phase-locked loop has been applied in practice, there has been a trade-off in terms of settling time, linearity of the modulation frequency response and reference frequency attenuation.

For example, in radiotelephone applications that require a small settling time and a linear modulation frequency response, the so-called a transfer oscillator system in which a modulated fixed transfer oscillator frequency is mixed with the receiver injection frequency. On the other hand, the transfer oscillator has the disadvantage of a large number of mixing results, which are difficult to attenuate. Another disadvantage is the complexity and cost of the connection.

The object of the present invention is to reduce the above-mentioned problems and to provide a connection which allows the use of modulated frequency synthesis even when it is required to have both a fast settling time and a low loop cut-off frequency.

3,79637

The invention is based on the solution of changing the gain of a phase-locked loop by adjusting the voltage of the pulses received from the digital phase comparator, whereby it is possible to use a high cut-off frequency, i.e. a fast loop during settlements and a low cut-off frequency after settling. Because no transfer oscillator system is used, no detrimental mixing results are generated.

When the gain of a phase-locked loop is changed in this way by changing the voltage of the pulses received from the digital phase comparator, changing the gain does not interfere with the operation of the loop.

In addition, the connection is simple and suitable for a commonly used two-output digital phase comparator and an operational amplifier-type integrator. If desired, the connection according to the invention also enables stepless control, and the control works flawlessly even with small phase differences.

The main features of the invention appear from the appended claim 1 and its preferred embodiments from the dependent claims 2-10.

Thus, according to the invention, the voltage of the pulses received from the digital phase comparator can be changed in the phase comparator or outside the phase comparator, for example by a diode, transistor, FET or some other voltage limiting circuit. The voltage limitation of the pulses can be implemented, for example, either in connection with the output of the phase comparator or by a circuit as described above built into the pulse filter. In the phase comparator, it is also possible to implement the control, for example, by changing the operating voltage of the phase comparator itself or its output stage.

* 79617

It is essential that the switching of the pulse in the connection can affect the gain of the phase-locked loop by changing the voltage and thus change e.g. loop cutoff frequency and speed.

It is also essential that when the gain of the loop is changed in this way by changing the voltage of the pulses received from the phase comparator, changing the gain does not interfere with the operation of the loop. In addition, the gain can be infinitely adjusted.

Thus, it is possible to use a high cut-off frequency, i.e. a fast loop, during settlements and to lower the cut-off frequency after settling without disturbing the operation of the loop.

In this way, a fast settling time as well as a linear modulation frequency response, low residual modulation and high reference frequency attenuation are obtained.

The circuit shown in the invention for adjusting the gain of a phase-locked loop can be used in several phase-locked applications, e.g. frequency synthesis, modulator or demodulator applications (e.g. AM, FM, PM), tracking filter, clock signal regeneration, etc.

Phase-locked loop gain control can be used in various applications, e.g., to adjust the loop cutoff frequency, accelerate and decelerate the loop, linearize the modulation frequency response, increase the reference frequency attenuation, or e.g., compensate for a change in loop gain as the division changes.

Other advantages of the connection are e.g. simplicity and cheapness, controllability of the adjustment, stepless adjustment and the fact that the gain adjustment does not interfere with the operation of the loop.

In addition, the connection shown can be applied to different types of digital phase detectors, e.g. single or dual output phase detectors.

5,79637

The application of the invention to an FM-modulated frequency synthesizer will be described in more detail below by way of example and with reference to the accompanying drawings, in which Figure 1 shows a block diagram of a phase-locked loop already described, Figure 2 shows a block diagram of , Fig. 4 shows pulse images related to Fig. 3, Fig. 5 shows frequency responses related to Fig. 3, Fig. 6 shows images related to claims 7 and 8, Fig. 7 shows images related to claims 8 and 9.

In the frequency synthesizer according to Fig. 2, a reference frequency is obtained from a stable crystal oscillator 4 (TCXO), the frequency of which is divided by a divider 2 (number R) to generate a suitable phase comparison frequency. The obtained phase reference frequency is applied to a phase comparator 1, the output signal of which is fed to a loop filter 2. This loop filter is a low-pass type filter in which AC components are filtered from the phase comparator signal and a DC voltage is supplied to the voltage controlled oscillator 3 (VCO). From the output of the voltage-controlled oscillator 3, the feedback is fed via a pre-divider 6 and a divider 7 to the second input of the phase comparator 1. When the frequency divider 7 (divisor N) of the feedback loop is made programmable, several frequencies can be synthesized by changing the divider N. The pre-divider 6 is used to drop the frequency of the voltage-controlled oscillator 3 to the operating range of the programmable divider 7, the frequency range of which is generally relatively small. At the same time, the output of the voltage-controlled oscillator 3 forms the output fout of the synthesizer.

β 79637

Since this connection is in principle well known to a person skilled in the art, it will not be described in more detail in this connection. Today, ready-made integrated circuits are available, which include, for example, dividers 5, a phase comparator 1 and a programmable divider 7, and such a circuit is denoted IC in Fig. 2.

Figure 3 shows a circuit according to the invention, in which the above-mentioned integrated circuit IC is of the type MC145156 (manufactured by Motorola).

This is thus a two-output phase comparator, the outputs of which are marked 0V and 0R in Fig. 3. These outputs are fed via resistors R5 and R6 to an integrator which, in the case of the figure, is a differential amplifier. using A.

Ko. the characteristic oscillation frequency fn of the phase-locked loop is 1 / K0 · Kvco ^ (1) fn «- / -

2 fr. / N · C · R

where K0 is the phase comparator gain 2iT * Afvco (2)

Kvco is - AVvco N is an integer division number (fout / fref) C is approximately C2 = C3 in Figure 3 and R is approximately R7 = R8 in Figure 3.

Changing K0 gives 7 79637 / κ02 ^ (3) fn2 = / · fnl V Κ01 i.e. the characteristic oscillation frequency of the loop is directly proportional to the square root of the phase comparator gain.

In the described case, the voltage of the pulses from the outputs 0V and 0R of the phase comparator is affected as follows:

For each output there is a resistor R5 resp. After R6, the cut-off transistors Q3 resp. Q2 emitters and transistor collectors are connected to the supply voltage Vdd (5 V). Normally a low cut-off frequency, i.e. a slow loop, is switched on, whereby capacitor C1 is charged through resistor R4 to +5 Vs and transistors Q2 and Q3 cut the voltage pulses of the phase comparator outputs 0V and 0R to 5 V pulses as shown in Fig. 4 at a is shown.

At the time of handover, when the division number information input to the programmable divider of the used circuit is activated, the activation pulse (TSEN) supplied to the terminal 13 of the circuit also provides control via the resistor R2 to the base of the switching transistor Q1. Then Q1 becomes momentarily conductive and the capacitor C1 is discharged through the resistor R3. Thus, the carrier voltage of transistors Q2 and Q3 drops to about 0 V and the height of the pulses on the emitters of the transistors momentarily rises to 5 V, as shown in Fig. 4 (b).

In this case, due to the increase of the loop gain, the cutoff frequency and speed of the loop also increase. Staying on the fast loop, i.e. high gain, depends on the time constant determined by the capacitor C1. In the case shown, the fast loop remains on for approximately 50 ms, during which time the loop has had time to settle.

8 79637

When the characteristic oscillation frequency of the phase-locked loop with the fast connection (fnl) shown is about 80 Hz, the characteristic oscillation frequency (fn2) of the slow loop is approximately 0.5 / 5 x 80 Hz, i.e. about 25 Hz. (K01. Kvco / N = 2300 Hz)

The diagram in Figure 5 shows the closed loop response of an example circuit with both fast and slow loops. Both the specific oscillation frequency fn of the loop and the cut-off frequency of -3 dB of the closed loop can be read from the response. In addition, FIG. the modulation frequency response of the loop with both fast and slow loop. The modulation frequency response remains direct in the desired range of 300 Hz to 10 kHz.

Claims (9)

9,79637 Patent Requirements A phase-locked loop circuit comprising, in series, a digital phase comparator (1), the second input of which is supplied with a comparator frequency (fref), a loop filter (2) and a voltage-controlled oscillator (3) from which a phase comparator is fed to the second input switching branch, characterized in that the voltage of the pulses obtained from the digital phase comparator (1) is adapted to be adjustable, whereby the limit limit and the speed of the phase-locked loop can be changed. A circuit according to claim 1, characterized in that the voltage of the pulses received from the digital phase comparator (1) is adapted to be regulated in the phase comparator itself or in its output stage, for example by adjusting the operating voltage. A circuit according to claim 1, characterized in that the voltage of the pulses obtained from the digital phase comparator (1) is adapted to be regulated by a diode, transistor or some other pulse voltage limiting circuit built outside the phase comparator. Switching according to Claims 2 and 3, characterized in that the voltage of the pulses received from the digital phase comparator is adjusted by using a higher loop cut-off frequency during settling (locking) and a lower cut-off frequency after settling. Switching according to Claims 2 and 3, characterized in that the voltage of the pulses received from the digital phase comparator (1) is adjusted with the loop locked in such a way that the gain and cut-off frequency of the loop change. 10 79637 Switching according to Claims 4 and 5, characterized in that the voltage of the pulses from the digital phase comparator (1) is adapted to be regulated or by adjusting the operating voltage of the pulse voltage changing (amplifying or attenuating) circuit connected between the output of the elevator and the loop filter. the voltage and thus the loop gain and cutoff frequency can be adjusted. Switching according to Claims 4 and 5, characterized in that the voltage of the two output pulses from the digital phase comparator is adapted to be regulated by a transistor cutter (Q4, Q5) built outside the phase comparator, the emitters of the transistors being connected to the outputs via resistors (R11, R12). 0R, 0V) and collectors to the supply voltage (+ Vdd), whereby by adjusting the base voltage (Us) it is possible to adjust the tree height on the emitters of the transistors and thus the gain and cut-off frequency of the loop. Switching according to Claims 4 and 5, characterized in that the voltage of the two output pulses from the digital phase comparator is adapted to be regulated by a diode cutter (D1, D2) built outside the phase comparator, in which the cathodes of the diodes are connected via resistors (R13, R14) or outputs. (0fR, 0V), whereby by adjusting the anode voltage (Us) of the diodes, the tree height at the cathodes of the diodes and thus the gain and cut-off frequency of the loop can be adjusted. Switching according to Claims 4 and 5, characterized in that one of the voltages of the output pulses from the digital phase comparator is adapted to be regulated by a transistor cutter (Q6, Q7) built outside the phase comparator, the transistor emitters being connected via a resistor (R15) to the phase comparator output (P15). and 11 79637 collector of NPN transistor (Q6) to operating voltage (+ Vdd) and collector of PNP transistor (Q7) to ground, whereby by adjusting the carrier voltages (Ua, Ub) of transistors (Q6, Q7) it is possible to adjust the pulse height of the transistor emitters and thus the cutoff frequency. A circuit according to claims 4 and 5, characterized in that the voltage of the pulses from the single-output digital phase comparator is adapted to be regulated by a diode cutter (D3, D4) built outside the phase comparator, wherein the cathode of the second diode (D3) and the anode of the second diode (D4) are connected via a resistor (R16) to the output (Pd) of the phase comparator, whereby by adjusting the anode voltage (Ua) of the second diode (D3) and the cathode voltage (Ub) of the second diode (D4), the pulse height and thus the loop gain and cutoff frequency can be adjusted.