KR970005395B1 - Phase-locked loop circuit - Google Patents

Abstract

No content.

Description

Phase locked loop circuit

1 is a block diagram of a phase locked loop.

2 is a block diagram of a frequency synthesizing apparatus composed of a phase locked loop.

3 shows an embodiment of a circuit according to the invention.

4 shows a pulse in relation to FIG.

5 shows the frequency response associated with FIG.

FIG. 6 relates to claims 19 and 20. FIG.

FIG. 7 relates to claims 20 and 21.

* Explanation of symbols for main parts of the drawings

1: digital phase comparator 2: loop filter

3: voltage controlled oscillator 4: stable crystal oscillator

5: Split element 6: Prescaler

7: frequency divider R11, R12, R13, R14, R15, R16: resistor

Q4, Q5, Q6, Q7: Transistors D1, D2, D3, D4: Diode

ψR, ψV, Pd: output of phase comparator

The present invention relates to a phase-locked loop circuit comprising a digital phase comparator supplied with a reference frequency to one input section, a loop filter, and a voltage controlled oscillator having a feedback branch connected to a second input section of the phase comparator. will be.

Such a phase locked loop is shown in block diagram in FIG. In the figure, the reference frequency f _ref is applied to the input of the phase comparator. The output of the phase comparator is connected to the loop filter 2 and this output is also connected to the voltage controlled oscillator 3. The output of the oscillator 3 is fed back to the phase comparator 1 to provide a loop, i.e. to set it to a constant ratio according to the reference frequency f _ref .

The use of such phase locked loops in frequency synthesizers is a recognized fact. When a phase locked loop is used for frequency synthesis in which the voltage controlled oscillator (VCO) is frequency modulated, a contradictory requirement arises for the loop ratio. If fast settling time is required when switching from one channel to another, the limit frequency of the loop should be as high as possible. In contrast, the limiting frequency must be low so that the loop does not make the modulation stronger or weaker, more precisely the limiting frequency must be much lower than the lowest modulation frequency. Additional advantages include low limiting frequency, which reduces residual modulation and increases attenuation of the phase reference frequency.

US Pat. Nos. 4,482,869 and 4,516,083 and EP 85615 disclose a method of accelerating a loop filter by removing a resistor or by changing the resistance value of the integrator of the filter by means of a short circuit. Correspondingly, deceleration is performed based on the removal of the short-circuit and the addition of the resistor. In U. S. Patent No. 4,156, 855, the current supplied to the integrator capacitor is increased with a current pump to further accelerate the loop.

However, by controlling the resistors with connectors, the operation of the loop is disturbed. Therefore, instantaneous tremors appear in the regulated voltage obtained from the VCO at the moment of connecting the slow loop, and thus cannot be tolerated when applied to a wireless telephone or the like. The same thing happens when the charge current in the integrator changes abruptly.

As a result, the frequency synthesis formed by the phase-locked loop is impossible to use without disturbing when fast settling time on the one hand and linear modulation frequency response on the other hand are required. When the modulation frequency synthesis formed by the phase locked loops is realized, they are traded off between set time and linear modulation frequency response and reference voltage attenuation.

For example, in applications such as wireless telephones where short settling time and linear modulation frequency response are required, the use of a so-called transmission oscillator system in which the modulation fixed transmission oscillator frequency is mixed with the receiver injection frequency is required. On the other hand, transmission oscillators have the drawback of producing numerous mixing results, which is difficult to attenuate. Another drawback is that the circuits are complex and expensive.

An object of the present invention is to solve different problems, and to provide a circuit that can use modulation frequency synthesis when fast settling time and low limit frequency of the loop are required.

The present invention is based on a solution involving gain modulation of a phase locked loop by adjusting the pulse voltage obtained from a digital phase comparator, the use of a high limiting frequency, i.e. the use of a rapid loop during setting and a low limiting frequency after setting. Can be used. Since no transmission oscillator system is used, no harmful mixing results are produced.

When modulating the gain of the phase locked loop by changing the pulse voltage obtained from the digital phase comparator, the change in gain does not interfere with the operation of the loop.

In addition, the circuit is simple, and is generally used for a digital phase comparator and op amp type integrator having two outputs. The circuit according to the invention allows stepless adjustment if required, which function without defect even with a slight phase difference.

The main features of the invention are shown in claim 11 and the preferred embodiments are shown in claims 12 to 22 which are dependent claims.

According to the present invention, the voltage of the pulse obtained from the digital phase comparator can be changed inside or outside the phase comparator by means of a diode, transistor, FET or limiting circuit that limits the voltage. The pulse voltage limit may be provided at the output of the phase comparator or may be provided in the loop filter as described above by circuit setting. In the phase comparator, adjustment can be performed by changing the power supply voltage of the phase comparator or by changing the power supply voltage of the output portion thereof.

By varying the pulse voltage in the circuit, the gain of the phase locked loop is affected, so that, among other things, the limiting frequency and ratio of the loop can be modulated.

Also, when changing the loop gain by modulating the voltage of the pulse obtained from the phase comparator, the change in gain does not interfere with the operation of the loop. In addition, the gain is adjustable steplessly.

Thus, it is possible to employ a high limiting frequency, i.e. a rapid loop during setting and to reduce the limiting frequency after setting without disturbing the operation of the loop.

In this way, fast settling time, linear modulation frequency response, and small residual modulation and large attenuation of the reference frequency are achieved.

The circuit of the present invention for adjusting the phase-locked loop gain can be applied to various phase-locked applications such as frequency synthesis, modulator (i.e., AM, FM, PM), tracking filter, clock signal regeneration, and the like.

The adjustment of the gain of the phase locked loop can be used in many applications.

That is, it is possible to adjust the limiting frequency of the loop, to accelerate and decelerate the loop, to linearize the modulation frequency response, to increase the reference frequency attenuation, or to compensate for the loop gain change when the divisor changes.

The circuit further has the advantage of providing simple and economical advantages, controllable adjustment, stepless adjustment, and the like, and the advantage that gain adjustment does not interfere with the operation of the loop.

The circuit can also be applied to various types of digital phase detectors, for example phase detectors with one or two outputs.

An example of applying the present invention to an FM modulated frequency synthesizer is described in detail below with reference to the accompanying drawings.

In the frequency synthesizing apparatus of FIG. 2, the reference frequency is provided by a stable crystal oscillator 4 (TCXO) in which the frequency is divided by the splitting element 5 (by the number R) to generate an appropriate phase comparison frequency. . The acquired phase comparison frequency is directed to the phase comparator 1, and the signal supplied by the output portion thereof is fed into the loop filter 2. This loop filter is a low pass filter in which the change component is filtered from the signal of the phase comparator and the DC voltage is obtained under the control of the voltage controlled oscillator 3 (VCO). A feedback is made from the output of the voltage controlled oscillator 3 through the prescaler 6 and the splitting element 7 to the second input of the phase comparator 1. When the frequency divider 7 of the feedback loop (divider N) is made programmable, a number of frequencies are synthesized by changing the divider N. The prescaler 6 is used to reduce the frequency of the voltage controlled oscillator 3 to the operating range of the programmable divider 7 with a relatively narrow frequency range. The output of the voltage controlled oscillator simultaneously forms F _out of the synthesizer output. This connection method is well known to those of ordinary skill in the art in principle, so detailed description thereof will be omitted. The complete integrated circuit available today consists of a splitting element 5, a phase comparator 1 and a programmable divider 7, denoted by reference numeral IC in the figure.

3 is a circuit according to the present invention, the integrated circuit (IC) used is MC 145156 type manufactured by Motorola.

This is therefore a phase comparator with two outputs, and the outputs are denoted by ψV and ψR in FIG. These outputs pass through resistors R5 and R6 and are applied to the integrator performed by the differential amplifier A.

Where Kψ is the gain of the phase comparator,

N is the entire divider (fout / fref), C is C2 = C3 for FIG. 3, and R is R7 = R8 for FIG.

By changing Kψ, the following equations are obtained.

In other words, the natural frequency of the loop is proportional to the square root of the gain of the phase comparator.

The voltage of the pulse obtained from the outputs ψV and ψR of the phase comparator is influenced as follows.

At both outputs, following the resistors R5 to R6, the emitters of the cutting transistors Q3 to Q2 and the collector of the transistors are connected to the supply voltage Vdd (5V). In the normal position, when the low limiting frequency, i.e. the slow loop is switched on, the capacitor C1 is charged to + 5V via the resistor R4 and the transistors Q2 and Q3 are connected to the 5V voltage of the outputs ψV and ψR. The pulse is split into pulses of about 0.5V, as shown at point a in FIG.

At the moment of switching the channel, since the visor information transferred into the programmable divider of the circuit in use is activated, the active pulse TSEN transferred into the terminal 14 of the microcircuit is also switched through the resistor R2 (the switch transistor ( The base of Q1) is controlled. Q1 is then electrically instantiated and the charge of capacitor C1 is discharged through resistor R3. Under these conditions, the base voltage of transistors Q2 and Q3 decreases to about 0V, and the height of the pulse on the emitter of the transistor rises to 5V instantaneously as illustrated at point b in FIG.

Increasing the loop gain also increases the limiting frequency and ratio of the loop. Keeping the rapid loop, ie high gain, depends on the time constant determined by capacitor C1. For example, the rapid loop remains switched on for about 5 ms long enough for the loop to settle.

In the case of the rapid loop, when the natural frequency (f _n1 ) of the phase-locked loop of the circuit is about 80 Hz, the natural frequency (f _n2 ) of the slow loop is about 0.5 / 5 × 80 Hz, that is, about 25 Hz (Kψ1, Kvco / N = 2300 Hz).

The curve in FIG. 5 illustrates the response of a synchronous loop of a sample circuit having a slow loop as well as a rapid loop. From these responses, it is possible to read the natural frequency f _n2 and the limit frequency of the synchronous loop (-3 dB). Also, the modulation frequency response of this loop is shown in FIG. 5 together with the rapid loop and the slow loop. The modulation frequency response is within the desired range (300Hz-10kHz).

6A and 6B show an external limiting circuit for limiting the output of a phase comparator with two outputs. FIG. 6A shows a transistor parameter with two transistors Q4 and Q5, each emitter being coupled to resistors R11 and R12. Each resistor is connected to the respective outputs ψR, ψV of the phase comparators. In addition, the collector of each transistor is connected to the power supply voltage Vdd. Thus, by varying the transistor's base voltage, the emitter voltage will be varied to adjust the output to the loop filter.

FIG. 6B shows a diode limiter for a phase comparator having two output units. The cathode of the first diode D1 is connected to the resistor R13, and the opposite terminal of the resistor R13 is connected to the output ψR of the phase comparator. The cathode of the second diode D2 is connected to the resistor R14, and the opposite terminal of the resistor R14 is connected to the output ψV of the phase comparator. By varying the voltage Us applied to the anode of the diode, the diode output regulates the output applied to the loop filter.

7A and 7B show an external limiting circuit for limiting the output of a phase comparator having one output. FIG. 7A shows a transistor limiter with two emitter connection transistors, both emitters connected to a resistor R15 and the opposite terminal of the resistor R15 to the output Pd of the phase comparator. The first transistor Q6 is an NPN transistor whose collector is connected to a power supply voltage Vdd, and the second transistor Q7 is a PNP transistor whose collector is connected to ground. Thus, by varying the voltages Ua and Ub applied to the bases of the respective transistors, the emitter voltages of the transistors are varied, thus adjusting the voltage supplied to the loop filter.

7B shows a diode limiter for controlling a phase comparator having one output unit. This circuit consists of two diodes (D3, D4). The cathode of the first diode D3 is connected to the anode of the second diode D4 and the resistor R16. The opposite terminal of the resistor is connected to the output Pd of the phase comparator. The output applied to the loop filter may be adjusted by adjusting the voltage Ua applied to the anode of the first diode D3 and the voltage Ub applied to the cathode of the second diode D4.

Claims (12)

A digital phase comparator 1 supplied with a reference frequency f _ref to a first input, a loop filter 2 for receiving the pulse voltage output of the phase comparator 10, and an output of the loop filter 2 A voltage controlled oscillator 3 for receiving and a feedback branch for connecting the output of the oscillator 3 to a second input of the phase comparator 1, and the limiting means Q2, Q3 comprise the digital phase comparator ( Connected directly to 1) and limiting the amplitude of the pulse voltage output of the phase comparator 1 in response to an external input signal TSEN applied to the limiting means, the external input signal determining bandwidth and locking ratio. A phase locked loop circuit, characterized in that. A phase locked loop circuit according to claim 1, wherein said limiting means is provided to said phase comparator (1). 2. A phase locked loop circuit according to claim 1, wherein said limiting means is provided by a limiting circuit external to said phase comparator (1). 4. The phase locked loop circuit according to claim 3, wherein the limiting circuit includes transistor parameters (Q2, Q3; Q4, Q5; Q6, Q7). 4. The phase locked loop circuit according to claim 3, wherein the limiting circuit includes diode limiters (D1, D2; D3, D4). 2. A phase locked loop circuit as claimed in claim 1, wherein said limiting means is operable to adjust the loop bandwidth so as to become large during the locking of the loop and smaller after the locking. 2. A phase locked loop circuit as claimed in claim 1, wherein said limiting means operates to adjust the bandwidth and gain of the loop while the loop is locked. 4. The phase locked loop circuit according to claim 3, wherein the pulse voltage output of said phase comparator (1) is adjustable by controlling the voltage supplied to said limiting circuit. 5. The phase comparator according to claim 4, wherein the phase comparator has two outputs (ψ R, ψ V), the limiting circuit comprises two transistors (Q4, Q5), and the emitter of each transistor has a respective resistance (R11, R12) is connected to the separate phase comparator output, and the collector of each transistor is connected to the supply voltage, so that the amount of change (Us) of the voltage applied to the base of each transistor is adjusted to output the emitter of each transistor. And adjusting the output voltage of the phase comparator. 6. The phase comparator according to claim 5, wherein the phase comparator has two outputs (ψR, ψV), the limiting circuit comprises two diodes (D1, D2), and the cathode of each diode has a respective resistance (R13, Connected to the separate phase comparator output via R14), the amount of change (Us) of the voltage applied to the anode of each diode adjusts the output of the cathode of each diode to adjust the phase comparator output voltage. Phase locked loop circuit. 5. The phase comparator of claim 4, wherein the phase comparator has one output Pd, and the limiting circuit comprises a first transistor Q6 and a second transistor Q7, and the emi of the first and second transistors. Is connected together to a phase comparator output via a resistor R15, the first transistor Q6 is an NPN transistor, its collector is connected to a power supply voltage, and the second transistor Q7 is a PNP transistor, and its collector. Is connected to the ground potential, the amount of change (U _a , U _b ) of the voltage applied to the base of each transistor adjusts the output of the emitter of each transistor to adjust the phase comparator output voltage. Phase locked loop circuit. The method of claim 5, wherein the phase comparator has one output (Pd), the limiting circuit comprises a first diode (D3) and a second diode (D4), the cathode of the first diode (D3) And the anode of the second diode D4 is connected to the phase comparator output through a resistor R16, whereby the amount of change of the voltage applied to the anode of the first diode and the cathode of the second diode (U _a , U _b ) And adjusts the voltage at the connection point of the first and second diodes to adjust the phase comparator output voltage.