FI95521C - Phase-locked loop - Google Patents

Description

, 95521

Phase locked loop - Fasläsningskrets

The present invention relates to a phase-locked loop comprising, in series, a phase comparator having a reference frequency applied to one input, a loop filter and a voltage controlled oscillator having a modulation signal applied to the second input and from which a feedback comparator branch is derived.

The invention also relates to a method implemented by a phase-locked loop.

The Phase Locked Loop (PLL) is shown in a block diagram in Figure 1. It introduces a reference frequency fref 15 to the input of the phase comparator 1. The output of the phase comparator is connected to the loop filter 2 and its output is further connected to the voltage controlled oscillator 3. The output of the oscillator 3 is connected back to the phase comparator 1 so that a loop is obtained which at a certain speed is set according to the reference frequency 20 fref.

It is well known to use such a phase-locked loop in e.g. frequency synthesizers. When a phase-locked loop is used in frequency synthesis, the voltage-controlled os-25 of a oscillator (VCO) is frequency modulated, a loop no- '·.? conflicting requirements. If a fast settling time is desired when switching from one channel to another, the cut-off frequency of the loop must be as high as possible. On the other hand, so that the loop does not emphasize or attenuate the modulation, the cut-off frequency of the loop should again be small, more specifically, the cut-off frequency should be much lower than the lowest modulation frequency. In addition, the low cut-off frequency has the advantage that the residual modulation is reduced and a higher attenuation is obtained for the phase reference frequency.

For example, it is known from U.S. Patents 4,482,869 and 4,516,083 and from EP Patent Application 85615 to speed up a loop filter by changing the resistance value of the filter integrator stage 35 95521 2 by either removing or shorting the resistors. Similarly, deceleration is based on removing short circuits or adding resistors. In U.S. Patent 4,156,855, the loop is further accelerated by increasing the current supplied to the condenser of the integrator stage by means of a current pump.

For example, in radiotelephone applications that require a small settling time and a linear modulation frequency response, the so-called a transmission oscillator-10 generator system in which a modulated fixed transmission oscillator frequency is mixed with a receiver injection frequency. However, a disadvantage of such a system is that the phase response of the modulation does not remain linear at low frequencies, in the vicinity of the cut-off frequency of the loop, because the loop 15 tends to change the modulation.

FI-79637 (U.S. Patent Application 698,483) discloses a circuit that allows the use of modulated frequency synthesis even when it requires both a fast settling time and a low loop cutoff frequency. The switching is based on the solution of changing the gain of the phase-locked loop by adjusting the voltage of the pulses from the digital phase comparator, making it possible to use a high cut-off frequency, i.e. a fast loop during settlements and a low cut-off frequency after settling.

In the connection, the pulse can be changed by changing the voltage to affect the gain of the phase-locked loop and thus change e.g. loop cutoff frequency and speed. 1 2 3 4 5 6

However, the disadvantage of this solution is that no- 2. , the main loop can only be used during settlements. chicken. In addition, there is an upper limit to the loop speed that 4 cannot be exceeded without the circuit becoming unstable, due to the inability of the phase comparator to supply enough 6 currents to the loop filter. From the upper speed limit of the loop, the support also becomes the lower limit for the settling time of the loop. In most cases, the settling time for the frequency and the lowest modulatable frequency are inconsistent, but can be reconciled with the characteristics required as a comp. In some systems, the inconsistency may be so great that the requirements cannot be met.

It is an object of the present invention to provide a phase locked loop which allows a higher cut-off frequency to be used without increasing the distortion caused by a fast loop filter. Since the use of a higher cut-off frequency allows a faster use of the loop filter, a faster frequency setting is achieved in the start-up situation. The invention is based on the solution that a phase equalizer is connected to the modulation line of the phase-locked loop, i.e. the modulation line of the voltage-controlled oscillator, which changes the phase behavior of the signal to be modulated in the opposite direction to the phase-locked loop. The invention is characterized in that a phase equalizer is connected to the modulation branch of the voltage-controlled oscillator before said modulation input of the voltage oscillator, which changes the phase behavior of the modulation signal in the opposite direction to the phase-locked loop and the magnitude of the change depends on the modulation frequency.

The application of the invention to a frequency modulated frequency synthesizer will be described in more detail below by way of example and with reference to the accompanying drawings, in which Fig. 1 shows a block diagram of a phase-locked loop already described, Fig. 2 shows 4 shows an implementation of a phase equalizer, Fig. 5 illustrates the effect of a phase equalizer on the phase of a modulation signal, Fig. 6 shows a 50 Hz rectangular wave generated by a PLL without a phase equalizer, Fig. 7 shows a 50 Hz rectangular wave generated by a PLL with a phase equalizer, 95 4 Fig. 8 shows a DSAT signal of a NAMPS system generated by a PLL without a phase equalizer, Fig. 9 shows a DSAT signal of a NAMPS system generated by a PLL with a phase equalizer, 5 Fig. 10 shows an eye of a DSAT signal of a NAMPS system generated by a PLL Fig. 11 shows an eye pattern of a DSAT signal of a PLAM-generated NAMPS system with a phase equalizer, Fig. 12 shows the amplitude and phase response of a voltage-controlled oscillator modulo-10 line without a phase equalizer, and Fig. 13 shows a voltage-controlled oscillator with a modulus-phase response amplifier.

In the frequency synthesizer according to Fig. 2, a reference frequency is obtained from a stable crystal oscillator 4 (TCXO), the frequency of which is divided by a divider 2 (number R) to generate a suitable phase reference frequency. The obtained phase comparison frequency is applied to a phase comparator 1, the output signal of which is fed to a loop filter 2. This loop filter is a low-pass type filter in which AC components are filtered from the phase comparator signal and a DC voltage .

From the output of the voltage-controlled oscillator 3, a feedback circuit is applied via a pre-divider 6 and a divider 7 to the second input of the phase comparator 1. When the frequency divider 7 (divider N) of the feedback loop is made programmable, several frequencies can be synthesized by changing the divider N. The pre-divider 30 is used to drop the frequency of the voltage-controlled oscillator 3 to the operating range of the programmable divider 7, which. the frequency range is usually relatively small. At the same time, the output of the voltage-controlled oscillator 3 forms the output fout of the synthesizer. The phase-locked loop provides the voltage-controlled oscillator 35 when locked to the frequency and phase of the reference signal to the phase comparator.

Il 95521 5

Since this connection is in principle well known to a person skilled in the art, it will not be described in more detail in this context. At present, ready-made integrated circuits are available, which include, for example, dividers 5, a phase comparator 5 and a programmable divider 7, and such a circuit is denoted IC in Fig. 2.

It was mentioned above that there are problems in modulating a phase locked loop at low frequencies. The loop tends to correct for changes in the voltage controlled oscillator, such as signal modulation. Below the cut-off frequency, the loop completely corrects all changes and at low frequencies the signal cannot be modulated due to this. On the other hand, if the cutoff frequency is increased, the distortions caused by the fast loop filter-15 to the frequency response increase. In the vicinity of the cut-off frequency above it, the signal can be modulated, although the loop tends to correct the modulation, but the loop is so slow that it does not have time to correct the changes completely and this is especially evident in the square waves as phase errors.

i

The phase-locked loop according to the invention can be used, for example, in the frequency synthesizer according to Fig. 2, which was described above. Figure 3 shows this hair-25 synthesizer in which, by connecting to the modulation line MOD

according to the invention, a phase equalizer 8 which changes the phase behavior of the signal to be modulated in the opposite direction to the phase-locked loop provides a more direct phase response and the situation appears to be slower for modulation, especially as less distortion of low frequency rectangular data. Distortion can be measured, for example, in the NAMPS system, the so-called by means of an eye pattern, which is described in more detail in connection with Figures 10 and 11. Thus, by using the step-35 loop according to the invention, a slightly higher limiting frequency can be used without substantially increasing distortions, and due to the higher limiting frequency, a faster loop filter can be used, resulting in a faster settling time.

95521 6

Figure 4 shows an alternative for implementing a phase equalizer. The structure is quite simple and consists of three star-connected resistors R1, R2 and R3 and one capacitor-C connected in series with the resistor R3, preferably a tantalum capacitor with one terminal connected to ground. The modulation signal enters the phase equalizer at the other terminal of the resistor R1 and the phase-corrected modulation signal is obtained as the phase equalizer output from the second terminal of the resistor R2. The connection of the phase equalizer is quite simple-10 times, and it is not new in itself. Phase equalizers (phase shifters) are already known to the person skilled in the art and can be implemented in several different ways and are therefore not considered in more detail here. The phase shift element shown here is implemented with passive components and acts as an integrator. Correspondingly, an active integrator or other active phase-shifting element containing an operational amplifier can also be used as the phase equalizer. The phase shifter usually has a fixed phase shift value depending on the structure used and the component values used. Thus, if it is desired to correct the modulation response according to the invention, the relative phase error of the modulation of the frequency synthesizer or phase-locked loop used must first be measured as a function of the modulation frequency or calculated by the loop shift function. Then, for example, a previously known phase equalizer is designed which changes the phase behavior of the modulation signal in the opposite direction to a phase-locked loop which tends to change the modulation, especially at low frequencies. The phase equalizer may include several phase shift elements, e.g., the elements shown in Figure 4, in order to achieve the desired phase shift.

Figure 5 illustrates a list of steps 4> sig of the modulation signal as a function of modulation frequency and a step equalizer step 4> phc and its effect on the modulation response 4> mod. A similar situation is shown in Figures 12 and 13. From the point of view of the invention, the absolute phase value at any frequency 95521 7 is not essential per se, but it is essential that the relative phase remains approximately constant. The phase-locked loop can be dimensioned according to the required settling time, and the minimum modulation frequency at which a sufficiently small phase error is still achieved to be used or for modulating the locked loop is some frequency f1. Often there is a need to use a lower modulation frequency, but then the phase errors increase as shown in the figure. A solution to the problem is to connect to the modulation line according to the invention a phase shifter which changes the phase of the modulation in the opposite direction to the phase-locked loop, especially at low frequencies, and whose phase response is shown in the figure as a curve S> phc. In this case, the combined effect of the modulation signal and the phase equalizer is to keep the modulation relatively constant in the phase-locked loop relative to the phase, even at low frequencies, whereby the modulation phase response <i> mod is approximately direct even at frequency f2 and higher frequencies (where f2 <). Thus, a lower modulation frequency can be used in the phase-locked loop, while the phase error still remains sufficiently small than without the phase shift performed.

Figures 6 and 7 show a 50 Hz rectangular wave generated by a phase-locked loop without a phase equalizer and 25 by a phase equalizer in a modulation line of a voltage-controlled oscillator with a phase-locked loop cut-off frequency of a few hertz. It can be seen from Figure 6 that the square wave 9 is distorted and not rectangular as desired, but the horizontal portions of the pulses are distorted. The corresponding wave 10 generated by the phase-locked loop according to the invention is rectangular, as shown in Fig. 7.

In a NAMPS mobile telephone system, a digital audio surveillance tone, called DSAT (Digital 35 Supervisory Audio Tone), is transmitted on the voice channel. The DSAT signal is generated at the base station and the mobile station responds to it, i.e. a closed loop is formed. The base station uses the DSAT signal to identify the mobile station. The DSAT signal rate is 100 8 95521 bit / s Manchester and 200 bit / s NRZ (non-return-to-zero) and the deviation is ± 700 Hz. Fig. 8 shows the DSAT signal 11 of the NAMPS system produced with a phase-locked loop without a phase equalizer in the modulation line, and in Fig. 9, respectively (curve 12) with a phase equalizer. Comparing Figures 8 and 9, it can be seen that by using a phase equalizer according to the invention, the variation of the DC level of the DSAT signal is reduced.

10 By feeding a pulse train through the transmission path, detecting the response with an oscilloscope and synchronizing it with an externally used pulse generator, an eye pattern of the pulse train is obtained on the image surface of the oscilloscope. The edges of the mesh pattern correspond to the worst possible interaction situation of the pulse train bit combinations. Figures 10 and 11 show the mesh pattern 13, 14 of the DSAT signal of the NAMPS system without a phase equalizer and with a phase equalizer. The eye pattern can be used to measure the distortion of the DSAT signal. Looking at Figures 10 and 11, one can see how much the eye pattern is ‘open’. This is shown in Fig. 20 as a percentage showing the height of the inner edge of the mesh pattern on the vertical axis delimited by the zero plane and the upper edge of the pattern. From the horizontal dashed line drawn in the figure, it can be seen that the mesh pattern 13 is 53.2% 'open' when no phase equalizer was used in the modulation line (Figure 10) and 73.8% 'open' when the phase equalizer was used in the modulation line (Figure 10). 11). The NAMPS system has a minimum requirement of 65% open in the outgoing signal and it can be seen that it does not meet this requirement in this example unless a phase equalizer is connected to the modulation line of the voltage controlled oscillator according to the invention.

Figures 12 and 13 show the measured amplitude A and phase response Φ of the modulation signal when there is no phase equalizer in the modulation line and when a phase equalizer is connected to the line according to the invention. Comparing the figures, it can be seen that the phase Φ changes quite sharply at low frequencies when there is no phase equalizer in the modulation line, while the phase response Φ is substantially straightened at low frequencies.

II

95521 9 using a phase equalizer according to the invention, as shown above in connection with Figure 5. It can be seen from this that by connecting the phase equalizer to the modulation line, a lower modulation frequency can be used. For the vertical axis as-5, each gap is in phase 10 ° and in amplitude 6 dB. The logarithmic frequency scale shown on the horizontal axis ranges from 10 Hz to 10 kHz.

The method according to the invention and the phase-locked loop 10 can be applied for various purposes in which a phase-locked loop is required or used, such as in a frequency synthesizer or a transfer oscillator. Accordingly, the invention is not limited to the examples set forth herein, but is applicable to various purposes within the scope of the claims.

Claims (10)

1. A phase reading circuit containing successively coupled a 3 phase detector (1), to each of whose inputs a reference 4 frequency (fref), a circuit filter (2) and a modulatable voltage controlled oscillator (3), 6 shows a modulation signal (MOD) and from which an feedback link has been fed to the second input of the phase detector (1), characterized in that the modulating branch (MOD) of the voltage controlled oscillator (3) has been connected before a voltage controlled oscillator. phase rectifier (8) which changes the phase behavior of the modulation signal (MOD) in the opposite direction relative to the phase reading circuit and the magnitude of the change is dependent on the modulation frequency (f). 5 Phase reading circuit according to claim 1, characterized in that the phase rectifier (8) comprises at least one phase shift element. Phase reading circuit according to claim 1, characterized in that the phase shifting element is an active circuit. 4. The phase reading circuit according to claim 1, characterized in that the phase shifting element is a passive circuit. 15 5. A phase reading circuit according to claim 4, characterized in that the phase shifting element comprises a resistor formed by resistor (R1, R2, R3), wherein the modulation signal is applied to one pole of the first resistor (R1) and the phase-corrected modulation signal (MOD) is attached from the second resistor. (R2) one pole and the third resistor (R3) are connected via a capacitor (C) to the ground. 6. A phase reading circuit according to claim 1, characterized in that it is part of a transmission oscillator. A phase reading circuit according to claim 1, characterized in that it is part of a frequency synthesizer. 1 2 3 4 5 6 8. A method for forming a phase reading circuit which is 2 modular with low frequencies, in which 3 - a reference frequency (fref) and from a voltage controlled 4 oscillator (3) received output signal is compared in a phase detector (1), 6 - the switch components is filtered from the phase detector (1) signal by a circuit filter (2) from which a direct voltage is obtained to control the voltage controlled oscillator - (3), and 95521 - the voltage controlled oscillator (3) is characterized by a modulation signal (MOD), characterized in that the phase (4) of the modulation signal (MOD) changes in the opposite direction to what the phase reading circuit changes on it and the magnitude of the change is dependent on the modulation frequency (f). 9. A method according to claim 8, characterized in that the phase of the modulation signal (MOD) (<t> fig) is changed at low frequencies in the opposite direction to what the phase reading circuit changes on it. Method according to Claim 8, characterized in that the phase ($) of the modulation signal (MOD) is changed in such a way that the relative phase of the modulation is essentially the same at high frequencies. (> · L ·