GB2267610A - Phase locked loop modulators - Google Patents

Abstract

The present invention relates to a phase-locked loop. comprising, connected in succession, a phase comparator (1), to one input of which a reference frequency (fref) is carried, a loop filter (2), and a voltage-controlled oscillator (3), to one input of which a modulation signal (MOD) is carried and from which a feedback branch is conducted to the other input of the phase comparator. To the modulation branch (MOD) of the voltage controlled oscillator (3) is connected a phase corrector (8) before said second input of the voltage oscillator, which changes the phase behaviour of the modulation signal (MOD) in a direction opposite to that effected by the phase-locked loop. The phase corrector may be in the form of an RC phase shifter. <IMAGE>

Description

Phase-locked loop The present invention relates to a phase-locked loop, comprising, connected in succession, a phase comparator, to one input of which a reference frequency is carried, a loop filter, and a voltage controlled oscillator, to one input of which a modulation signal is carried and from which a feedback branch to the other input of the phase comparator has been conducted. The invention also relates to a method implemented by the phase locked loop.

A Phase Locked Loop is shown as a block diagram in Fig. 1. Reference frequency fref is carried to the input of a phase comparator 1. The output of the phase comparator has been connected to a loop filter 2, and the output thereof furthermore to a voltage controlled oscillator 3. The output of the oscillator 3 is fed back to the phase comparator 1 so that a loop is formed which at a given rate is set according to the reference frequency fref It is well known in the art to use this kind of phase locked loop e.g. in frequency synthesizers. When a phase locked loop is used in a frequency synthesis in which a voltage controlled oscillator is frequency modulated, creating contradictory demands concerning the settling time of the loop. When a short settling time is desired in moving from one channel to another, the cutoff frequency of the loop must be as high as possible. On the other hand, for the loop not to intensify nor suppress the modulation, the cut-off frequency of the loop should be low, and to be quite accurate, the cut-off frequency should be a lot lower than the lowest modulation frequency. A low cut-off frequency is useful also in that sense that the residual modulation reduces and for the phase reference frequency a greater attenuation can be provided.

For instance, it is known in the US. Patents Nos. 4,482,869 and 4,516,083 as well as in EP Patent No. 85615 to accelerate the loop filter by changing resistor rate of the integrator degree of the filter either by removing resistors or by shortcircuiting. Similarly, the deceleration is based on the removal of the shortcircuits or on addition of resistors. In the US. Patent No. 4,156,855, the loop is further accelerated by increasing the power supplying the capacitor of the integrator stage with the aid of a current pump.

For instance in radio telephone applications in which a fast settling time and a linear modulation frequency response are required, it is often necessary to use a so-called transfer oscillator system in which a modulated fixed transfer oscillator frequency is mixed with the receiver injection frequency. A drawback in said system is however that the phase response of modulation will not remain linear at low frequencies in the adjacency of the cut-off frequency of the loop because the loop tends to change the modulation.

In Patent No. FI-79 637 (US. Patent application No. 698,483) a circuit is disclosed for enabling the use of modulated frequency synthesis also when it is required to possess both a fast settling time and a low cut-off frequency of the loop. The circuit is based on a design in which the amplification of a phaselocked loop is changed by setting the voltage of the pulses obtained from the digital phase comparator, whereby a high cut-off frequency, i.e. fast loop, can be used during the settings, and a low cut-off frequency after the setting. In a circuit the amplification of the phase-locked loop can be affected by changing the pulse voltage and therethrough e.g. the cut-off frequency and speed of the loop can be changed.

A drawback of said design is however that a fast loop can be used only during settling. There is also an upper limit in the rapidity of the loop which cannot be exceeded without making the circuit unstable, said feature being caused by the fact that the phase comparator is not capable of supplying enough current to the loop filter. Because of the speed upper limit of the loop, also a lower limit exists in the settling time of said loop. As regards the frequency, the setting time and the lowest modulatable frequency are most often in contradiction, but they are adaptable to form a compromise between the requisite characteristic features. In some systems the contradiction can be so great that the requirements cannot be met.

According to a first aspect of the present invention there is provided a phaselocked loop, comprising a phase comparator, having an input for receiving a reference frequency (f), a filter, and a voltage controlled oscillator (VCO) having a modulation signal (MOD) input and from which VCO an output signal is able to be fed back to another input of the phase comparator, wherein a phase compensator is electrically coupled to the modulation signal (MOD) input of the VCO to adapt the phase behaviour of the modulation signal (MOD) in order to compensate for effects of the phase-locked loop.

In a second aspect of the present invention there is provided a method for phase-locking a signal to be modulated at low frequencies, comprising: - comparing a reference frequency (free) and a signal derived from a voltagecontrolled oscillator in a phase comparator, - passing a signal output from the phase comparator through a filter thereby obtaining the voltage for controlling the voltage controlled oscillator, - modulating the voltage controlled oscillator with a modulation signal (MOD), and - changing the phase ( b5tg ) of the modulation signal to compensate for the phase-locked loop.

The first and second aspects of the invention have the advantage that it is possible to have a higher loop filter cut-off frequency without increasing the phase distortion caused by such a fast loop filter. Since the higher cut-off frequency results in a faster loop filter, a shorter settling time is possible.

In a preferred embodiment of the first aspect of the invention the phase compensator comprises at least one phase shifting element. This has the advantage that it is a relatively simple and straightforward way of implementing the invention.

Suitably the phase shifting element may be an active circuit or a passive circuit, which has the advantage that the particular characteristics and functions of the two types of phase shifting circuit can be best matched to the overall system requirements.

Advantageously, the passive circuit comprises first, second and third resistors connected in a star configuration and wherein the modulation signal is input to a free terminal of the first resistor, a phase-compensated modulation signal is present on a free terminal of the second resistor and the third resistor is coupled to ground via a capacitor, which is a convenient and straightforward implementation of a phase-shifting element.

A specific embodiment of the invention is hereinafter described by way of an example only and referring to the accompanying drawings in which: Fig. 1 shows a block diagram of a conventional phase-locked loop; Fig. 2 shows a block diagram of a frequency synthesizer including a phaselocked loop; Fig. 3 shows a block diagram of a frequency synthesizer according to the invention; Fig. 4 shows an implementation of a phase corrector; Fig. 5 shows the effect of the phase corrector on the phase of a modulation signal; Fig. 6 shows a 50Hz square wave generated with a PLL, without a phase corrector; Fig. 7 shows a 50Hz square wave generated with a PLL, with a phase corrector; Fig. 8 shows a DSAT signal of the NAMPS system generated with a PLL, without a phase corrector; Fig. 9 shows a DSAT signal of the NAMPS system generated with a PLL, with a phase corrector; Fig. 10 shows the loop figure of the DSAT signal of the NAMPS system generated with a PLL, without a phase corrector; Fig. 11 shows the loop figure of the DSAT signal of the NAMPS system generated with PLL, with a phase corrector; Fig. 12 shows the amplitude and phase response of the modulation line of a voltage controlled oscillator, without a phase corrector; and Fig. 13 shows the amplitude and phase response of the modulator line of a voltage controlled oscillator, with a phase corrector.

In a frequency synthesizer as shown in Fig. 2 the reference frequency is derived from a stable crystal oscillator 4 (TCXO). This frequency is then divided by a dividing element 5 (with number R) to create an appropriate phase comparison frequency. The phase comparison frequency thus obtained is carried to a phase comparator 1, and the output signal from the phase comparator is fed to a loop filter 2. The loop filter is a low pass filter which filters the alternating components from the signal output from the phase comparator. The resulting D.C. voltage can be amplified to a desired level appropriate to control a voltage controlled oscillator 3. The output of the voltage controlled oscillator 3 is fed back to a second input of the phase comparator 1 via a pre-divider 6 and a dividing element 7. When the frequency divider 7 of the feedback loop (division number N) is made programmable, a great number of frequencies can be synthesized by changing the division number N. The predivider 6 is used to reduce the frequency of the voltage controlled oscillator 3 to the operation range of the programmable divider 7, the frequency range of which is usually low. At the same time, the output of the voltage-controlled oscillator 3 constitutes the output fout of the synthesizer.

With the aid of the phase-locked loop the voltage-controlled oscillator can be made to lock with the frequency and the phase of the reference signal entering the phase comparator.

The principle of such a circuit is well known to those skilled in the art and therefore is not described in great detail in the present context. Such preintegrated circuits are currently available which include e.g. dividing eleme nts 5, a phase comparator 1 and a programmable divider 7; one such circuit is marked with reference IC in Fig. 2.

It is mentioned above that a number of problems arise in modulating the phaselocked loop at low frequencies. The loop tends to correct the changes carried to the voltage-controlled oscillator, such as the modulation of a signal. Below the cut-off frequency the loop corrects all changes completely and, for this reason, the signal cannot be modulated at low frequencies. On the other hand, if the cut-off frequency is increased, the distortions caused on the frequency response by a fast loop filter become greater. Close to the cut-off frequency, the signal can be modulated although the loop makes attempts to correct the modulation but the loop is however so slow that the changes cannot be corrected completely therethrough, and this is seen particularly in the square waves as phase errors.

A phase-locked loop in accordance with the invention can be used e.g. in the frequency synthesizer as shown in Fig. 2 in the manner described above. Fig.

3 shows such a frequency synthesizer in which, by connecting a phase corrector 8 to the modulation line MOD to change the phase behaviour of the signal to be modulated in opposite direction to that effected by the phaselocked loop, a more linear phase response is obtained. With respect to the modulation, the situation seems such as if the loop filter were slower, and this is seen particularly as a smaller distortion of low-frequency rectangular data.

The distortion can be measured e.g. in the NAMPS system with the aid of a so-called eye pattern, referred to in more detail in association with Figs 10 and 11. Therefore, using a phase-locked loop according to the invention a somewhat larger cut-off frequency can be used without any substantially increased distortions, and because of a higher cut-off frequency, a faster loop filter can be used, whereby a faster settling time is obtained.

Fig. 4 shows one way of implementing the phase corrector. The structure is quite simple and it consists of three star-connected resistors R1, R2 and R3, and one capacitor C, preferably a tantalum capacitor, connected in series with resistor R3, and having one terminal grounded. A modulation signal enters the other terminal of the resistor R1 of the phase corrector, and the phase-corrected modulation signal is derived from the other terminal of the resistor R2 in the form of output of the phase corrector. The connection of the phase corrector is quite simple and is not new in itself. The phase correctors (phase shifters) are known to those skilled in the art, and they can be implemented in a number of ways, and for that reason, they will not be discussed any further in the present context. The phase shifting element mentioned here is implemented with passive components and it serves as an integrator. Similarly, e.g. an active integrator comprising an operational amplifier or other active phase shifting elements can be used as a phase corrector. The phase shifter usually has a fixed phase shifting value dependent on the design and the component values used. Thus, if one wants to correct the modulation response to conform to the invention, the relative phase error of the modulator of the frequency synthesizer or the phase-locked loop must first be measured as a function of the modulation frequency, or said error must be calculated with the aid of the shift function of the loop. Then e.g. a phase corrector is cqnnected to the modulation line, being so designed that it changes the phase behaviour of the modulation signal in a direction opposite to that effected by the phaselocked loop, said loop having the tendency of changing the modulation, especially at low frequencies. The phase corrector may comprise a number of phase shifting elements, such as those presented in Fig. 4, in order to reach a desired phase shift.

Fig. S illustrates a relative phase P, of the modulation signal as a function of the modulation frequency and a phase bph of the phase corrector, and its effect on the modulation response iP,,. An equivalent situation is presented in Figs 12 and 13. With regard to the invention, the absolute phase value at a frequency is not essential in itself, but the essential feature is to maintain the relative phase somewhere near a constant. The phase-locked loop can be dimensioned according to a required setting time, and the lowest modulation frequency at which an adequate small phase error can still be reached, so that it can be used for modulation of a phase-locked loop, is any frequency fl.

There is often need to use a lower modulation frequency but in such instances the phase errors get bigger and bigger, as is seen in figure 5. A solution to the problem according to the invention is to connect a phase shifter to the modulation line to change the modulation phase in a direction opposite to that effected by the phase-locked loop, particularly at low frequencies, and in which the phase response thereof is represented as a curve bph in the figure.

Thereby, the modulation can be maintained, in the form of a combined effect of the modulation signal and the phase corrector, in the loop phase-locked in the relative phase thereof approximately as a constant also at low frequencies (where f2 < fl). Thus, a lower modulation frequency can be used in the phase-locked loop when the phase error remains sufficiently small than without the phase shift carried out.

Figs 6 and 7 respectively show a 50 Hz square wave generated with a phaselocked loop without a phase corrector, and a phase-locked loop with a phase corrector, in the modulation line of a voltage controlled oscillator in which the limit frequency of the phase-locked loop is a few Hz. Fig. 6 shows that the square wave 9 is distorted and not rectangular, and has the horizontal portions of the pulses distorted. An equivalent wave 10 produced with the phase-locked loop according to the invention is rectangular, as is shown in Fig. 7.

In the NAMPS mobile phone system a Digital Supervisory Audio Tone, the so-called DSAT signal, is transmitted in the speech channel. The DSAT signal is generated in a base station and a mobile station sends a response thereto, i.e.

a closed loop is created. The base station uses the DSAT signal for identifying the mobile station. The rate of the DSAT signal is 100 bit/s Machester and 200 bit/s NRZ, and the deviation + 700 Hz. Fig. 8 shows a DSAT signal 11 of the NAMPS system produced with the aid of a phase-locked loop without a phase corrector in the modulation line, and figure 9 shows it with a phase corrector (curve 12). When Figs 8 and 9 are compared, it can be seen that using the phase corrector as according to the invention, a DC level variation in the DSAT signal has been reduced.

By feeding a pulse queue through a shift route, by displaying the response on an oscilloscope, synchronized to an external pulse generator, the eye pattern of the pulse queue can be produced on the display of the oscilloscope. The margins of the eye pattern correspond to the worst possible mutual effect situation of the bit combinations of the pulse queue. Figs. 10 and 11 respectively show the eye image 13 and 14 of the DSAT signal of the NAMPS system without a phase corrector and with a phase corrector. With the aid of the eye pattern the distortion of the DSAT signal can be measured. As in Figs 10 and 11, it is seen how much the eye pattern is 'open'. This is presented as a percentage in the figure showing the height of the inner edge of the eye pattern on the vertical axis defined by the zero level and the upper edge of the figure.

With the horizontal broken line in figure 10 it can be seen that the eye pattern 13 is 'open' by 53.2% when no phase corrector is used in the modulation line and 'open' by 73.8% when a phase corrector was used in the modulation line as shown in figure 11. The minimum requirement in the NAMPS system is a 65 % open state in the output signal, and it can be seen that it will not meet the requirement in the present example if no phase corrector is connected to the modulation line of a voltage-controlled oscillator.

Figs 12 and 13 respectively show a measured amplitude response A and phase response of a modulation signal when no phase corrector is included in the modulation line, and when a phase corrector is connected to the line. On comparing the figures it can be seen that the phase b changes rather steeply at low frequencies when no phase corrector is included in the modulation, whereas the phase response has been substantially linearized at low frequencies when a phase corrector is used. Thus it is seen that when a phase corrector is connected to the modulation line a lower modulation frequency can be used.

The method and the phase-locked loop according to the invention can be applied to various purposes, in which a phase-locked loop is needed or used, such as in a frequency synthesizer or in a shift oscillator. The invention is not therefore confined to the examples described above, but it can be applied to various purposes within the scope of the claims below.

The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicity or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigates any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom.

Claims (13)

Claims

1. A phase-locked loop, comprising a phase comparator, having an input for receiving a reference frequency (fuzz a filter, and a voltage controlled oscillator (VCO) having a modulation signal (MOD) input and from which VCO an output signal is able to be fed back to another input of the phase comparator, wherein a phase compensator is electrically coupled to the modulation signal (MOD) input of the VCO to adapt the phase behaviour of the modulation signal (MOD) in order to compensate for effects of the phaselocked loop.

2. Phase-locked loop according to claim 1, wherein the phase compensator comprises at least one phase shifting element.

3. Phase-locked loop according to claim 2, wherein the phase shifting element is an active circuit.

4. Phase-locked loop according to claim 2, wherein the phase shifting element is a passive circuit.

5. Phase-locked loop according to claim 4, wherein the passive circuit comprises first, second and third resistors connected in a star configuration and wherein the modulation signal is input to a free terminal of the first resistor, a phase-compensated modulation signal is present on a free terminal of the second resistor and the third resistor is coupled to ground via a capacitor.

6. A phase-locked loop substantially as hereinbefore described and with reference to the drawings of figures 3 to 13.

7. A shift oscillator comprising a phase-locked loop according to any preceding claim.

8. A frequency synthesizer comprising a phase-locked loop according to any preceding claim.

9. A method for phase-locking a signal to be modulated at low frequencies, comprising: - comparing a reference frequency (fref) and a signal derived from a voltagecontrolled oscillator in a phase comparator, - passing a signal output from the phase comparator through a filter thereby obtaining the voltage for controlling the voltage controlled oscillator, - modulating the voltage controlled oscillator with a modulation signal (MOD), and - changing the phase (b5g) of the modulation signal to compensate for the phase-locked loop.

10. A method according to claim 9, wherein at low frequencies the phase (b5,g) of the modulation signal (MOD) is adapted to be changed in a direction opposite to a change caused by the phase-locked loop.

11. A method according to claim 10, wherein the phase (b5,g) of the modulation signal (MOD) is changed so that the relative phase of the modulation is substantially the same at low and high frequencies.

12. A phase-locked loop, comprising, connected in succession, a phase comparator (1), to one input of which a reference frequency (free) is carried, a loop filter (2), and a voltage controlled oscillator (3) to be modulated, to which a modulation signal (MOD) is also carried and from which a feedback branch is conducted to the other input of the phase comparator (1), characterized in that a phase corrector (8) has been connected to the modulation branch (MOD) of the voltage controlled oscillator (3) before the voltage oscillator to change the phase behaviour of the modulation signal (MOD) in a direction opposite to that effected by the phase-locked loop.

13. A procedure for producing a phase-locked loop to be modulated at low frequencies, in which - a reference frequency (fuzz and an output signal derived from a voltagecontrolled oscillator (3) are compared in a phase comparator (1), - alternating components are filtered from the signal of the phase comparator (1) with a loop filter (2) from which the direct voltage is obtained for controlling the voltage controlled oscillator (3), and - the voltage controlled oscillator (3) is modulated with a modulation signal (MOD), characterised in that - the phase (iP,i, ) of the modulation signal is changed in a direction opposite to that changed by the phase-locked loop.