FI4318618T3 - Suprajohtava laite, suprajohtavan laitteen valmistusmenetelmä ja laminoitu runko - Google Patents

Suprajohtava laite, suprajohtavan laitteen valmistusmenetelmä ja laminoitu runko

Info

Publication number
FI4318618T3
FI4318618T3 FIEP21932866.3T FI21932866T FI4318618T3 FI 4318618 T3 FI4318618 T3 FI 4318618T3 FI 21932866 T FI21932866 T FI 21932866T FI 4318618 T3 FI4318618 T3 FI 4318618T3
Authority
FI
Finland
Prior art keywords
electrode
metal
forming
substrate
hole
Prior art date
Application number
FIEP21932866.3T
Other languages
English (en)
Finnish (fi)
Inventor
Makoto Nakamura
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of FI4318618T3 publication Critical patent/FI4318618T3/fi

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/82—Current path
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Containers, Films, And Cooling For Superconductive Devices (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
FIEP21932866.3T 2021-03-22 2021-03-22 Suprajohtava laite, suprajohtavan laitteen valmistusmenetelmä ja laminoitu runko FI4318618T3 (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/011752 WO2022201253A1 (ja) 2021-03-22 2021-03-22 超電導デバイス、超電導デバイスの製造方法及び積層体

Publications (1)

Publication Number Publication Date
FI4318618T3 true FI4318618T3 (fi) 2025-10-17

Family

ID=83395369

Family Applications (1)

Application Number Title Priority Date Filing Date
FIEP21932866.3T FI4318618T3 (fi) 2021-03-22 2021-03-22 Suprajohtava laite, suprajohtavan laitteen valmistusmenetelmä ja laminoitu runko

Country Status (6)

Country Link
US (1) US20240237557A1 (https=)
EP (1) EP4318618B1 (https=)
JP (1) JP7563578B2 (https=)
CN (1) CN116897616A (https=)
FI (1) FI4318618T3 (https=)
WO (1) WO2022201253A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12588147B2 (en) * 2022-11-09 2026-03-24 Micron Technology, Inc. Filling cracks on a substrate via
WO2024111061A1 (ja) * 2022-11-22 2024-05-30 富士通株式会社 装置および装置の製造方法
US12550635B2 (en) 2023-05-17 2026-02-10 International Business Machines Corporation Controlling TLS via on-chip filtering to prevent qubit energy loss
WO2025046715A1 (ja) * 2023-08-28 2025-03-06 富士通株式会社 量子ビットデバイス及び量子ビットデバイスの製造方法
JP2026028554A (ja) * 2024-08-07 2026-02-20 富士通株式会社 デバイスの製造方法及びデバイス

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029165B2 (ja) * 1977-02-08 1985-07-09 三菱電機株式会社 超電導化合物線およびその製造方法
JPH0269994A (ja) * 1988-09-05 1990-03-08 Mitsubishi Mining & Cement Co Ltd セラミック超伝導体多層配線基板およびその製造方法
JP3118562B2 (ja) * 1997-12-08 2000-12-18 工業技術院長 超電導集積回路構造及びその製造方法
US9836699B1 (en) * 2015-04-27 2017-12-05 Rigetti & Co. Microwave integrated quantum circuits with interposer
US10242968B2 (en) * 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
SG11201805152UA (en) 2015-12-15 2018-07-30 Google Llc Superconducting bump bonds
US10291231B2 (en) * 2016-07-20 2019-05-14 Microsoft Technology Licensing, Llc Superconducting device with dummy elements
US10325870B2 (en) 2017-05-09 2019-06-18 International Business Machines Corporation Through-substrate-vias with self-aligned solder bumps

Also Published As

Publication number Publication date
CN116897616A (zh) 2023-10-17
EP4318618B1 (en) 2025-09-10
EP4318618A4 (en) 2024-06-05
JP7563578B2 (ja) 2024-10-08
US20240237557A1 (en) 2024-07-11
EP4318618A1 (en) 2024-02-07
JPWO2022201253A1 (https=) 2022-09-29
WO2022201253A1 (ja) 2022-09-29

Similar Documents

Publication Publication Date Title
FI4318618T3 (fi) Suprajohtava laite, suprajohtavan laitteen valmistusmenetelmä ja laminoitu runko
US4571664A (en) Solid electrolyte capacitor for surface mounting
KR101792287B1 (ko) 집적된 박막 배터리를 갖는 인쇄 회로 보드
US3404319A (en) Semiconductor device
JPWO2022201253A5 (https=)
JP2001203316A5 (https=)
JP2016111332A (ja) パッケージ構造およびその製造方法
US9870931B2 (en) Package carrier and manufacturing method thereof
CN106744656A (zh) 一种微机电系统器件封装方法及结构
CN106783788A (zh) 具有布线迹线的半导体封装
KR20080003795A (ko) 접합-절연 비아들
US9704747B2 (en) Semiconductor device and manufacturing method thereof
US2989669A (en) Miniature hermetically sealed semiconductor construction
CN100459083C (zh) 内埋元件的基板制造方法
US7525140B2 (en) Integrated thin film capacitors with adhesion holes for the improvement of adhesion strength
JP2015133387A5 (https=)
US10714268B2 (en) Solid electrolytic capacitor
US20120314377A1 (en) Packaging structure embedded with electronic elements and method of fabricating the same
US9437367B2 (en) Method of manufacturing a winding-type solid electrolytic capacitor package structure without using a lead frame
US7662726B2 (en) Integrated circuit device having a gas-phase deposited insulation layer
JP2012099518A (ja) 貫通電極基板
US9252114B2 (en) Semiconductor device grid array package
US7696083B2 (en) Multi-layer device
JPS63291439A (ja) 半導体搭載用基板および半導体パッケ−ジ
CN109196610A (zh) 薄膜器件以及薄膜器件的制造方法