JPWO2022201253A1 - - Google Patents

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Publication number
JPWO2022201253A1
JPWO2022201253A1 JP2023508173A JP2023508173A JPWO2022201253A1 JP WO2022201253 A1 JPWO2022201253 A1 JP WO2022201253A1 JP 2023508173 A JP2023508173 A JP 2023508173A JP 2023508173 A JP2023508173 A JP 2023508173A JP WO2022201253 A1 JPWO2022201253 A1 JP WO2022201253A1
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JP
Japan
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JP2023508173A
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Japanese (ja)
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JP7563578B2 (ja
JPWO2022201253A5 (https=
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Publication of JPWO2022201253A1 publication Critical patent/JPWO2022201253A1/ja
Publication of JPWO2022201253A5 publication Critical patent/JPWO2022201253A5/ja
Application granted granted Critical
Publication of JP7563578B2 publication Critical patent/JP7563578B2/ja
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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • H10N60/82Current path
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0912Manufacture or treatment of Josephson-effect devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/12Josephson-effect devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/021Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211Through-semiconductor vias, e.g. TSVs
    • H10W20/213Cross-sectional shapes or dispositions
    • H10W20/2134TSVs extending from the semiconductor wafer into back-end-of-line layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Containers, Films, And Cooling For Superconductive Devices (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
JP2023508173A 2021-03-22 2021-03-22 超電導デバイス、超電導デバイスの製造方法及び積層体 Active JP7563578B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/011752 WO2022201253A1 (ja) 2021-03-22 2021-03-22 超電導デバイス、超電導デバイスの製造方法及び積層体

Publications (3)

Publication Number Publication Date
JPWO2022201253A1 true JPWO2022201253A1 (https=) 2022-09-29
JPWO2022201253A5 JPWO2022201253A5 (https=) 2023-09-12
JP7563578B2 JP7563578B2 (ja) 2024-10-08

Family

ID=83395369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023508173A Active JP7563578B2 (ja) 2021-03-22 2021-03-22 超電導デバイス、超電導デバイスの製造方法及び積層体

Country Status (6)

Country Link
US (1) US20240237557A1 (https=)
EP (1) EP4318618B1 (https=)
JP (1) JP7563578B2 (https=)
CN (1) CN116897616A (https=)
FI (1) FI4318618T3 (https=)
WO (1) WO2022201253A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12588147B2 (en) * 2022-11-09 2026-03-24 Micron Technology, Inc. Filling cracks on a substrate via
WO2024111061A1 (ja) * 2022-11-22 2024-05-30 富士通株式会社 装置および装置の製造方法
US12550635B2 (en) 2023-05-17 2026-02-10 International Business Machines Corporation Controlling TLS via on-chip filtering to prevent qubit energy loss
WO2025046715A1 (ja) * 2023-08-28 2025-03-06 富士通株式会社 量子ビットデバイス及び量子ビットデバイスの製造方法
JP2026028554A (ja) * 2024-08-07 2026-02-20 富士通株式会社 デバイスの製造方法及びデバイス

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397798A (en) * 1977-02-08 1978-08-26 Mitsubishi Electric Corp Superconductive compound wire and production of the same
JPH0269994A (ja) * 1988-09-05 1990-03-08 Mitsubishi Mining & Cement Co Ltd セラミック超伝導体多層配線基板およびその製造方法
JPH11177157A (ja) * 1997-12-08 1999-07-02 Agency Of Ind Science & Technol 超電導集積回路構造及びその製造方法
JP2019504511A (ja) * 2015-12-15 2019-02-14 グーグル エルエルシー 超伝導バンプボンド
JP2020520090A (ja) * 2017-05-09 2020-07-02 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9836699B1 (en) * 2015-04-27 2017-12-05 Rigetti & Co. Microwave integrated quantum circuits with interposer
US10242968B2 (en) * 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
US10291231B2 (en) * 2016-07-20 2019-05-14 Microsoft Technology Licensing, Llc Superconducting device with dummy elements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397798A (en) * 1977-02-08 1978-08-26 Mitsubishi Electric Corp Superconductive compound wire and production of the same
JPH0269994A (ja) * 1988-09-05 1990-03-08 Mitsubishi Mining & Cement Co Ltd セラミック超伝導体多層配線基板およびその製造方法
JPH11177157A (ja) * 1997-12-08 1999-07-02 Agency Of Ind Science & Technol 超電導集積回路構造及びその製造方法
JP2019504511A (ja) * 2015-12-15 2019-02-14 グーグル エルエルシー 超伝導バンプボンド
JP2020520090A (ja) * 2017-05-09 2020-07-02 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造

Also Published As

Publication number Publication date
CN116897616A (zh) 2023-10-17
EP4318618B1 (en) 2025-09-10
EP4318618A4 (en) 2024-06-05
JP7563578B2 (ja) 2024-10-08
FI4318618T3 (fi) 2025-10-17
US20240237557A1 (en) 2024-07-11
EP4318618A1 (en) 2024-02-07
WO2022201253A1 (ja) 2022-09-29

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