FI118240B - Förfarande och anordning för dekodning av yttre sammankedjade CRC-koder - Google Patents

Förfarande och anordning för dekodning av yttre sammankedjade CRC-koder Download PDF

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Publication number
FI118240B
FI118240B FI991971A FI19991971A FI118240B FI 118240 B FI118240 B FI 118240B FI 991971 A FI991971 A FI 991971A FI 19991971 A FI19991971 A FI 19991971A FI 118240 B FI118240 B FI 118240B
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Finland
Prior art keywords
data
frame
crc
decoded
bits
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FI991971A
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English (en)
Finnish (fi)
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FI19991971A (sv
Inventor
Jeremy Stein
Ayal Bar-David
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Qualcomm Inc
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25234442&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=FI118240(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of FI19991971A publication Critical patent/FI19991971A/sv
Application granted granted Critical
Publication of FI118240B publication Critical patent/FI118240B/sv

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4115—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors list output Viterbi decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Artificial Intelligence (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Catalysts (AREA)

Claims (9)

1. Apparat för bestämning av datahastigheten hos en dataram, vilken dataram omfattar digitalt data 5 kodat med en av flera olika datahastigheter, vilket digitalt data omfattar informationsbitar och tillhörande kontrollbitar da apparaten omfattar: kombineringsmedel (222, 422) för kombinering av 10 dataramens digitala data för producering av kombinerat data beroende pä varje olika datahastighet; gallerdekodermedel (224, 424) för dekodning av kombinerat data genom identifiering av en optimal 15 rutt därigenom för producering av dekodat data; valideringsmedel (232, 432) för validering av det dekodade datat, som representerar nämnda informationsbitar och tillhörande kontrollbitar, genom användning av de tillhörande kontrollbitarna 20 och ger en indikation om datats validitet; * ’ kännetecknad därav, att ·· » · : ** gallerdekodningsmedlen (224, 424) är anordnade att « « * * * · *·* * identifiera suboptimala rutter därigenom som har * * ett eget mätt inom en förutbestämd tröskel för en * · · ·.· * 25 motsvarande optimal rutt och att ge dekodat data • * · V * motsvarande varje identifierad suboptimal rutt; valideringsmedlen (232,432) är anordnade att : **· validera det dekodade datat för varje identif ierad • · · suboptimal rutt och producera en indikation pä ϊ 30 dess validitet; och ♦ · · ' · * · ramens datahastighet är vald att motsvara den rutt »Il för vilken valideringsmedlen (232, 432) ger en • · ' • · 1. valid indikering. * · · • · * * 32 118240
2. Apparat enligt patentkrav 1, kännetecknad därav, att nämnda valideringsmedel (232, 432) omfattar , medel för cyklisk redundanskontroll (CRC) av nämnda kontrollbitar i förhällande till de nämnda ; 5 informationsbitar.
3. Apparat enligt patentkrav 2, kännetecknad därav, att den vidare omfattar medel för cyklisk redundanskontroll (CRC) av nämnda suboptimala 10 rutt.
4. Apparat enligt vilket tidigare patentkrav som heist, kännetecknad därav, att nämnda medel för dekodning (224, 424) är en Viterbi-dekoder. 15
5. Apparat enligt vilket tidigare patentkrav som heist, kännetecknad därav, att nämnda mätt är Yamamoto-mätt. , 20
6. System för bestämning av datahastigheten hos en • · · · · * · ,, dataram, vilken dataram omfattar digitalt data som • · · . -Λ *... är kodat med en av flera olika datahastigheter • * · * [ vilket digitalt data omfattar informationsbitar och tillhörande kontrollbitar, kännetecknat därav, • · · 25 att systemet omfattar en apparat enligt vilket som • t * * heist av de tidigare patentkraven. ·· • f
7. Förfarande för bestämning av datahastigheten hos • · *·;·* en dataram, vilken dataram omfattar digitalt data • · ·,· j 30 kodat med en av flera olika datahastigheter, * * * ‘ i vilket digitalt dataomfattar intormationsbitar och • · · —1 .**♦. tillhörande kontrollbitar, dä förfarandet • · • · · omfattar: • ♦ • · kombinering av dataramens digitala data beroende j 118240 33 pii var och en av de olika hastigheterna for producering av kombinerat data; galledekodning av kombinerat data genom identifiering av en optimal rutt därigenom för 5 producering av dekodat data; validering av det dekodade datat, som representerar nämnda informationsbitar och tillhörande kontrollbitar, genom användning av de tillhörande kontrollbitarna och givande av en 10 indikering av datats validitet; kännetecknat av ! identifiering av suboptimala rutter därigenom som har ett eget mätt inom en förutbestämd tröskel för en motsvarande optimal rutt och givande av dekodat 15 data motsvarande var och en av de identifierade j ' · · .·> suboptimala rutterna; ; validering av dekodat data för varje identifierad suboptimal rutt och givande av en indikation pä dess validitet; 20 vai av en datahastighet för ramen motsvarande * # + ··· • 1 rutten för vilken validitetsindikationen gavs. ♦ · • 1 * ·♦ * • · · *.1 1
8. Förfarande enligt patentkrav 7, kännetecknat * 1 därav, att valideringen av det dekodade datat »·· *.1 1 25 omfattar en cyklisk redundanskontroll för • · · V ' kontrollbitarna i förhällande till informationsbitarna. • · • ·# • · ·
9. Förfarande enligt patentkrav 8, kännetecknat • 30 därav, att det vidare omfattar en cyklisk • · · · redundanskontroll för de suboptimala rutterna. • · · • · • · • · 1 · · • · · . • · • ·
FI991971A 1997-03-21 1999-09-16 Förfarande och anordning för dekodning av yttre sammankedjade CRC-koder FI118240B (sv)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/821,845 US6094465A (en) 1997-03-21 1997-03-21 Method and apparatus for performing decoding of CRC outer concatenated codes
US82184597 1997-03-21
US9805706 1998-03-20
PCT/US1998/005706 WO1998043360A1 (en) 1997-03-21 1998-03-20 List output viterbi decoding with crc outer code for multi-rate signal

Publications (2)

Publication Number Publication Date
FI19991971A FI19991971A (sv) 1999-11-22
FI118240B true FI118240B (sv) 2007-08-31

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Application Number Title Priority Date Filing Date
FI991971A FI118240B (sv) 1997-03-21 1999-09-16 Förfarande och anordning för dekodning av yttre sammankedjade CRC-koder

Country Status (19)

Country Link
US (1) US6094465A (sv)
EP (1) EP0970566B1 (sv)
JP (1) JP3998726B2 (sv)
KR (1) KR100634071B1 (sv)
CN (1) CN1265787A (sv)
AT (1) ATE241874T1 (sv)
AU (1) AU6769798A (sv)
BR (1) BR9809566A (sv)
CA (1) CA2284638C (sv)
DE (1) DE69815087T2 (sv)
DK (1) DK0970566T3 (sv)
ES (1) ES2203938T3 (sv)
FI (1) FI118240B (sv)
HK (1) HK1026528A1 (sv)
ID (1) ID24973A (sv)
IL (1) IL131907A0 (sv)
PT (1) PT970566E (sv)
RU (1) RU99122351A (sv)
WO (1) WO1998043360A1 (sv)

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PT970566E (pt) 2003-10-31
CA2284638A1 (en) 1998-10-01
BR9809566A (pt) 2000-07-04
DE69815087D1 (de) 2003-07-03
CN1265787A (zh) 2000-09-06
JP3998726B2 (ja) 2007-10-31
KR20010005541A (ko) 2001-01-15
ATE241874T1 (de) 2003-06-15
RU99122351A (ru) 2001-08-27
EP0970566A1 (en) 2000-01-12
DE69815087T2 (de) 2004-04-01
ID24973A (id) 2000-08-31
KR100634071B1 (ko) 2006-10-13
CA2284638C (en) 2007-07-24
DK0970566T3 (da) 2003-09-22
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WO1998043360A1 (en) 1998-10-01
HK1026528A1 (en) 2000-12-15
IL131907A0 (en) 2001-03-19
AU6769798A (en) 1998-10-20
FI19991971A (sv) 1999-11-22
US6094465A (en) 2000-07-25

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