ES538400A0 - Sistema de control de memoria intermedia para un microprocesador - Google Patents

Sistema de control de memoria intermedia para un microprocesador

Info

Publication number
ES538400A0
ES538400A0 ES538400A ES538400A ES538400A0 ES 538400 A0 ES538400 A0 ES 538400A0 ES 538400 A ES538400 A ES 538400A ES 538400 A ES538400 A ES 538400A ES 538400 A0 ES538400 A0 ES 538400A0
Authority
ES
Spain
Prior art keywords
microprocessor
control system
memory control
intermediate memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES538400A
Other languages
English (en)
Other versions
ES8606694A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES538400A0 publication Critical patent/ES538400A0/es
Publication of ES8606694A1 publication Critical patent/ES8606694A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
ES538400A 1983-12-09 1984-12-07 Sistema de control de memoria intermedia para un microprocesador Expired ES8606694A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58233103A JPS60124754A (ja) 1983-12-09 1983-12-09 バッファ記憶制御装置

Publications (2)

Publication Number Publication Date
ES538400A0 true ES538400A0 (es) 1986-04-01
ES8606694A1 ES8606694A1 (es) 1986-04-01

Family

ID=16949818

Family Applications (1)

Application Number Title Priority Date Filing Date
ES538400A Expired ES8606694A1 (es) 1983-12-09 1984-12-07 Sistema de control de memoria intermedia para un microprocesador

Country Status (9)

Country Link
US (1) US4751638A (es)
EP (1) EP0145594B1 (es)
JP (1) JPS60124754A (es)
KR (1) KR900004890B1 (es)
AU (1) AU552118B2 (es)
BR (1) BR8406289A (es)
CA (1) CA1221172A (es)
DE (1) DE3484500D1 (es)
ES (1) ES8606694A1 (es)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184753A (ja) * 1984-10-01 1986-04-30 Hitachi Ltd バツフアメモリ
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US4896258A (en) * 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
US5117489A (en) * 1987-04-22 1992-05-26 Mitsubishi Denki Kabushiki Kaisha Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet
WO1989000313A1 (en) * 1987-07-01 1989-01-12 Unisys Corporation Fast-tag transfer improvement
JP2806930B2 (ja) * 1987-10-20 1998-09-30 富士通株式会社 主記憶一致制御方式
DE69033438T2 (de) * 1989-04-13 2000-07-06 Sandisk Corp Austausch von fehlerhaften Speicherzellen einer EEprommatritze
US7447069B1 (en) 1989-04-13 2008-11-04 Sandisk Corporation Flash EEprom system
US7190617B1 (en) * 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
JPH035851A (ja) * 1989-06-01 1991-01-11 Fujitsu Ltd バッファ記憶装置
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
US5028186A (en) * 1990-01-29 1991-07-02 Mechanical Plastics Corp. Hollow wall anchor with enhanced holding strength
US10254961B2 (en) * 2017-02-21 2019-04-09 International Business Machines Corporation Dynamic load based memory tag management

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982231A (en) * 1972-03-31 1976-09-21 International Business Machines Corporation Prefixing in a multiprocessing system
JPS596415B2 (ja) * 1977-10-28 1984-02-10 株式会社日立製作所 多重情報処理システム
JPS5849945B2 (ja) * 1977-12-29 1983-11-08 富士通株式会社 バツフア合せ方式
CH638731A5 (de) * 1979-07-11 1983-10-14 Schweizerische Lokomotiv Schienenfahrzeug.
JPS5619575A (en) * 1979-07-25 1981-02-24 Fujitsu Ltd Data processing system having hierarchy memory
US4467414A (en) * 1980-08-22 1984-08-21 Nippon Electric Co., Ltd. Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
JPS589273A (ja) * 1981-07-07 1983-01-19 Nec Corp デ−タ処理装置
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache

Also Published As

Publication number Publication date
EP0145594A3 (en) 1988-07-27
AU552118B2 (en) 1986-05-22
KR900004890B1 (en) 1990-07-09
JPH0319976B2 (es) 1991-03-18
CA1221172A (en) 1987-04-28
DE3484500D1 (de) 1991-05-29
EP0145594B1 (en) 1991-04-24
ES8606694A1 (es) 1986-04-01
EP0145594A2 (en) 1985-06-19
AU3627284A (en) 1985-06-13
JPS60124754A (ja) 1985-07-03
KR850004822A (ko) 1985-07-27
BR8406289A (pt) 1985-10-08
US4751638A (en) 1988-06-14

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20001202