ES473001A1 - Perfeccionamientos en memorias integradas solamente de lec- tura - Google Patents

Perfeccionamientos en memorias integradas solamente de lec- tura

Info

Publication number
ES473001A1
ES473001A1 ES473001A ES473001A ES473001A1 ES 473001 A1 ES473001 A1 ES 473001A1 ES 473001 A ES473001 A ES 473001A ES 473001 A ES473001 A ES 473001A ES 473001 A1 ES473001 A1 ES 473001A1
Authority
ES
Spain
Prior art keywords
conductors
memory
bit
integrated
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES473001A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of ES473001A1 publication Critical patent/ES473001A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)

Abstract

Perfeccionamientos en memorias integradas solamente de lectura especialmente para circuitos integrados semiconductores para almacenar información, cuyas memorias solamente de lectura tienen una formación de matriz de conductores de palabras y bitios aislados en sus intersecciones, estando definida la información almacenada por un modelo de elementos en intersecciones elegidas, para cambiar el voltaje en el conductor de bitios en respuesta a una señal en el conductor de palabras correspondiente, siendo el modelo el necesario para que exista por lo menos un lugar de conductor de palabras en el cual haya de haber una secuencia de intersecciones sucesivas en las que no existen elementos de cambio de voltaje, extendiéndose la secuencia de intersecciones desde un extremo terminal del lugar del conductor de palabras en la formación de matriz hasta uno de dichos elementos, caracterizados porque el conductor de palabras en el lugar del conductor de palabras mencionado termina físicamente en dicho elemento inmediatamente antes de la secuencia de intersecciones exponiendo por lo tanto los lugares de los conductores de palabras entre la terminación física del conductor de palabras y el extremo terminal del lugar del conductor de palabras en el borde de la formación de matriz y obteniéndose espacio disponible en el circuito integrado semiconductor.
ES473001A 1977-08-31 1978-08-31 Perfeccionamientos en memorias integradas solamente de lec- tura Expired ES473001A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/829,570 US4139907A (en) 1977-08-31 1977-08-31 Integrated read only memory

Publications (1)

Publication Number Publication Date
ES473001A1 true ES473001A1 (es) 1979-10-16

Family

ID=25254888

Family Applications (1)

Application Number Title Priority Date Filing Date
ES473001A Expired ES473001A1 (es) 1977-08-31 1978-08-31 Perfeccionamientos en memorias integradas solamente de lec- tura

Country Status (7)

Country Link
US (1) US4139907A (es)
EP (1) EP0001164B1 (es)
JP (1) JPS5812678B2 (es)
CA (1) CA1118099A (es)
DE (1) DE2861509D1 (es)
ES (1) ES473001A1 (es)
IT (1) IT1099314B (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2545047C3 (de) * 1975-10-08 1978-09-21 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur Herstellung eines Halbleiterfestwertspeichers
JPS55163859A (en) * 1979-06-07 1980-12-20 Fujitsu Ltd Manufacture of semiconductor device
US4318014A (en) * 1979-07-27 1982-03-02 Motorola, Inc. Selective precharge circuit for read-only-memory
US4356413A (en) * 1980-08-20 1982-10-26 Ibm Corporation MOSFET Convolved logic
US4402043A (en) * 1980-11-24 1983-08-30 Texas Instruments Incorporated Microprocessor with compressed control ROM
DE3177249D1 (de) * 1980-11-24 1991-08-08 Texas Instruments Inc Pseudo-mikroprogrammsteuerung in einem mikroprozessor mit komprimiertem steuerfestwertspeicher und mit bandanordnung von sammelschienen, alu und registern.
DE3824823A1 (de) * 1988-07-21 1990-01-25 Langer Ruth Geb Layher Anschlussausbildung fuer horizontaltraeger von geruestboeden
DE102013004974A1 (de) * 2013-03-21 2014-09-25 Infineon Technologies Ag Integrierte Schaltungsanordnung, Verfahren und System zum Einsatz in einer sicherheitskritischen Anwendung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB981104A (en) * 1963-01-10 1965-01-20 Standard Telephones Cables Ltd Improvements in or relating to logical circuit assemblies
GB1101851A (en) * 1965-01-20 1968-01-31 Ncr Co Generalized logic circuitry
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder
US3529299A (en) * 1966-10-21 1970-09-15 Texas Instruments Inc Programmable high-speed read-only memory devices
US3721964A (en) * 1970-02-18 1973-03-20 Hewlett Packard Co Integrated circuit read only memory bit organized in coincident select structure
GB1300301A (en) * 1970-04-20 1972-12-20 Gen Instr Microelect Read-only memories
GB1348361A (en) * 1971-05-05 1974-03-13 Mo Lesotekhnichesky I Read-only memory
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits
JPS5732438B2 (es) * 1973-07-27 1982-07-10
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals
US3987287A (en) * 1974-12-30 1976-10-19 International Business Machines Corporation High density logic array
US3975623A (en) * 1974-12-30 1976-08-17 Ibm Corporation Logic array with multiple readout tables

Also Published As

Publication number Publication date
JPS5812678B2 (ja) 1983-03-09
IT7827164A0 (it) 1978-08-30
DE2861509D1 (en) 1982-02-25
US4139907A (en) 1979-02-13
CA1118099A (en) 1982-02-09
EP0001164A1 (en) 1979-03-21
IT1099314B (it) 1985-09-18
JPS5447534A (en) 1979-04-14
EP0001164B1 (en) 1982-01-06

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20010301