ES455336A1 - Mejoras introducidas en un sistema para la regeneracion de informacion vinaria codificada. - Google Patents

Mejoras introducidas en un sistema para la regeneracion de informacion vinaria codificada.

Info

Publication number
ES455336A1
ES455336A1 ES455336A ES455336A ES455336A1 ES 455336 A1 ES455336 A1 ES 455336A1 ES 455336 A ES455336 A ES 455336A ES 455336 A ES455336 A ES 455336A ES 455336 A1 ES455336 A1 ES 455336A1
Authority
ES
Spain
Prior art keywords
data stream
recovery system
data recovery
frequency deviations
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES455336A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Corp filed Critical Sperry Corp
Publication of ES455336A1 publication Critical patent/ES455336A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Mejoras introducidas en un sistema para la regeneración de información binaria codificada que está representada en un flujo de datos en unas posiciones de tiempo que recurren a una frecuencia normalmente predeterminada, pero sometida a variaciones incontrolables, incluyendo el sistema unos medios para generar señales que tienen porciones altas y bajas alternativamente para ser utilizadas como ventanas de regeneración, una lógica de regeneración alimentada con dichas ventanas, y un bucle de oscilador sincronizado en fase controlado por un comparador de fase y que determina los momentos de ocurrencia de las ventanas, aplicándose al comparador de fase, dos señales de comparación una que está constituida por la señal de realimentación del bucle, mientras que la otra es una señal derivada del flujo de datos, estando dichas mejoras caracterizadas porque incluyen: un dispositivo para suministrar a la lógica de regeneración una señal también derivada del flujo de datos y que tiene características variables en función del tiempo representativas de la información que se produce sustancialmente al mismo tiempo que unas características variables en función el tiempo correspondientes, de dicha señal derivada a partir del flujo de datos que se suministra al comparador de fase, y ello de manera sustancialmente independiente de dichas variaciones de frecuencia.
ES455336A 1976-01-29 1977-01-25 Mejoras introducidas en un sistema para la regeneracion de informacion vinaria codificada. Expired ES455336A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/653,410 US4017803A (en) 1976-01-29 1976-01-29 Data recovery system resistant to frequency deviations

Publications (1)

Publication Number Publication Date
ES455336A1 true ES455336A1 (es) 1978-01-01

Family

ID=24620771

Family Applications (1)

Application Number Title Priority Date Filing Date
ES455336A Expired ES455336A1 (es) 1976-01-29 1977-01-25 Mejoras introducidas en un sistema para la regeneracion de informacion vinaria codificada.

Country Status (9)

Country Link
US (1) US4017803A (es)
JP (1) JPS5294112A (es)
CA (1) CA1051528A (es)
CH (1) CH620068A5 (es)
DE (1) DE2703395C3 (es)
ES (1) ES455336A1 (es)
FR (1) FR2340000A1 (es)
GB (1) GB1565245A (es)
IT (1) IT1075058B (es)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2748075C3 (de) * 1977-10-26 1980-08-07 Siemens Ag, 1000 Berlin Und 8000 Muenchen Phasenregelkreis
DE2823343B1 (de) * 1978-05-29 1979-08-16 Siemens Ag Verfahren und Anordnung zur Taktsignalrueckgewinnung bei digitaler Signaluebertragung
US4222009A (en) * 1978-11-02 1980-09-09 Sperry Corporation Phase lock loop preconditioning circuit
US4357707A (en) * 1979-04-11 1982-11-02 Pertec Computer Corporation Digital phase lock loop for flexible disk data recovery system
BR8004455A (pt) * 1979-07-19 1981-01-27 Exxon Research Engineering Co Circuito separador de dados e circuito para emprego na recuperacao de um sinal de relogio de um sinal codificado de dados dos
US4339823A (en) * 1980-08-15 1982-07-13 Motorola, Inc. Phase corrected clock signal recovery circuit
US4400667A (en) * 1981-01-12 1983-08-23 Sangamo Weston, Inc. Phase tolerant bit synchronizer for digital signals
US4371974A (en) * 1981-02-25 1983-02-01 Rockwell International Corporation NRZ Data phase detector
US4456890A (en) * 1982-04-05 1984-06-26 Computer Peripherals Inc. Data tracking clock recovery system using digitally controlled oscillator
JPS58182323A (ja) * 1982-04-20 1983-10-25 Nec Corp 位相同期回路
BE895439R (nl) * 1982-12-22 1983-06-22 Int Standard Electric Corp Impulscorrectieketen en schakelingen die er gebruik van maken
US4556866A (en) * 1983-03-16 1985-12-03 Honeywell Inc. Power line carrier FSK data system
US4547738A (en) * 1983-06-10 1985-10-15 American Standard Inc. Phase shift demodulator
NL8401310A (nl) * 1984-04-24 1985-11-18 Philips Nv Inrichting voor het opwekken van een kloksignaal.
US4682343A (en) * 1984-09-11 1987-07-21 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Processing circuit with asymmetry corrector and convolutional encoder for digital data
US4633488A (en) * 1984-11-13 1986-12-30 Digital Equipment Corporation Phase-locked loop for MFM data recording
US4847876A (en) * 1986-12-31 1989-07-11 Raytheon Company Timing recovery scheme for burst communication systems
US4879730A (en) * 1988-05-31 1989-11-07 Siemens Transmission Systems, Inc. Jitter tolerant circuit for dual rail data
JP2512786B2 (ja) * 1988-07-18 1996-07-03 富士通株式会社 位相整合回路
US4975930A (en) * 1988-11-02 1990-12-04 Digital Equipment Corporation Digital phase locked loop
US5579348A (en) * 1994-02-02 1996-11-26 Gi Corporation Method and apparatus for improving the apparent accuracy of a data receiver clock circuit
US5892797A (en) * 1996-07-17 1999-04-06 Jay Deng System and method for recovering data encoded using manchester code and other bi-phase level codes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3825844A (en) * 1972-10-18 1974-07-23 Peripherals General Inc System for recovering phase shifted data pulses

Also Published As

Publication number Publication date
JPS6227470B2 (es) 1987-06-15
JPS5294112A (en) 1977-08-08
FR2340000A1 (fr) 1977-08-26
IT1075058B (it) 1985-04-22
FR2340000B1 (es) 1982-12-31
US4017803A (en) 1977-04-12
DE2703395B2 (de) 1978-03-23
GB1565245A (en) 1980-04-16
DE2703395C3 (de) 1978-11-23
DE2703395A1 (de) 1977-08-04
CA1051528A (en) 1979-03-27
CH620068A5 (es) 1980-10-31

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