ES418485A1 - Disposicion de estructura de circuito integrado de aisla- miento de multiples capas. - Google Patents

Disposicion de estructura de circuito integrado de aisla- miento de multiples capas.

Info

Publication number
ES418485A1
ES418485A1 ES418485A ES418485A ES418485A1 ES 418485 A1 ES418485 A1 ES 418485A1 ES 418485 A ES418485 A ES 418485A ES 418485 A ES418485 A ES 418485A ES 418485 A1 ES418485 A1 ES 418485A1
Authority
ES
Spain
Prior art keywords
layer
openings
contacts
regions
circuit structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES418485A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US298729A external-priority patent/US3877051A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES418485A1 publication Critical patent/ES418485A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
ES418485A 1972-10-18 1973-09-05 Disposicion de estructura de circuito integrado de aisla- miento de multiples capas. Expired ES418485A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US298729A US3877051A (en) 1972-10-18 1972-10-18 Multilayer insulation integrated circuit structure

Publications (1)

Publication Number Publication Date
ES418485A1 true ES418485A1 (es) 1976-04-16

Family

ID=23151792

Family Applications (1)

Application Number Title Priority Date Filing Date
ES418485A Expired ES418485A1 (es) 1972-10-18 1973-09-05 Disposicion de estructura de circuito integrado de aisla- miento de multiples capas.

Country Status (5)

Country Link
JP (1) JPS5428073B2 (2)
DD (1) DD109476A5 (2)
ES (1) ES418485A1 (2)
IT (1) IT1001545B (2)
SE (1) SE386308B (2)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor

Also Published As

Publication number Publication date
JPS5428073B2 (2) 1979-09-13
IT1001545B (it) 1976-04-30
JPS4975065A (2) 1974-07-19
SE386308B (sv) 1976-08-02
DD109476A5 (2) 1974-11-05
SE7312846L (2) 1974-04-19

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