ES367720A1 - Un metodo de montar un sistema microelectronico unitario. - Google Patents

Un metodo de montar un sistema microelectronico unitario.

Info

Publication number
ES367720A1
ES367720A1 ES367720A ES367720A ES367720A1 ES 367720 A1 ES367720 A1 ES 367720A1 ES 367720 A ES367720 A ES 367720A ES 367720 A ES367720 A ES 367720A ES 367720 A1 ES367720 A1 ES 367720A1
Authority
ES
Spain
Prior art keywords
clips
mould
block
terminal pads
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES367720A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Friden Inc
Original Assignee
Friden Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Friden Inc filed Critical Friden Inc
Publication of ES367720A1 publication Critical patent/ES367720A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
ES367720A 1967-05-15 1969-05-27 Un metodo de montar un sistema microelectronico unitario. Expired ES367720A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US63853667A 1967-05-15 1967-05-15

Publications (1)

Publication Number Publication Date
ES367720A1 true ES367720A1 (es) 1971-04-16

Family

ID=24560432

Family Applications (1)

Application Number Title Priority Date Filing Date
ES367720A Expired ES367720A1 (es) 1967-05-15 1969-05-27 Un metodo de montar un sistema microelectronico unitario.

Country Status (9)

Country Link
US (1) US3489952A (en:Method)
BE (1) BE715204A (en:Method)
CH (1) CH472120A (en:Method)
DE (1) DE1766392A1 (en:Method)
ES (1) ES367720A1 (en:Method)
FR (1) FR1578928A (en:Method)
GB (1) GB1165854A (en:Method)
NL (1) NL6806852A (en:Method)
SE (1) SE334654B (en:Method)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3604099A (en) * 1969-08-18 1971-09-14 Western Electric Co Methods of and apparatus for bonding leaded devices to substrates
US3672046A (en) * 1970-01-14 1972-06-27 Technitrol Inc The method of making an electrical component
US3919602A (en) * 1972-03-23 1975-11-11 Bosch Gmbh Robert Electric circuit arrangement and method of making the same
US3774078A (en) * 1972-03-29 1973-11-20 Massachusetts Inst Technology Thermally integrated electronic assembly with tapered heat conductor
US3777220A (en) * 1972-06-30 1973-12-04 Ibm Circuit panel and method of construction
US3959874A (en) * 1974-12-20 1976-06-01 Western Electric Company, Inc. Method of forming an integrated circuit assembly
US4392181A (en) * 1981-05-01 1983-07-05 Western Electric Company, Inc. Circuit board and contact assemblies
US4514784A (en) * 1983-04-22 1985-04-30 Cray Research, Inc. Interconnected multiple circuit module
US4559272A (en) * 1984-05-09 1985-12-17 Hughes Aircraft Company Heat curable polyglycidyl aromatic amine encapsulants
US4780795A (en) * 1986-04-28 1988-10-25 Burr-Brown Corporation Packages for hybrid integrated circuit high voltage isolation amplifiers and method of manufacture
US5444600A (en) * 1992-12-03 1995-08-22 Linear Technology Corporation Lead frame capacitor and capacitively-coupled isolator circuit using the same
US7927920B2 (en) * 2007-02-15 2011-04-19 Headway Technologies, Inc. Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package
US7816176B2 (en) * 2007-05-29 2010-10-19 Headway Technologies, Inc. Method of manufacturing electronic component package
DE102009001371A1 (de) * 2009-03-06 2010-09-09 Hilti Aktiengesellschaft Handgeführtes Eintreibgerät
US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2629802A (en) * 1951-12-07 1953-02-24 Rca Corp Photocell amplifier construction
US3029495A (en) * 1959-04-06 1962-04-17 Norman J Doctor Electrical interconnection of miniaturized modules
GB1058296A (en) * 1963-06-28 1967-02-08 Rca Corp Composite insulator-semiconductor wafer and method of making same
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3262022A (en) * 1964-02-13 1966-07-19 Gen Micro Electronics Inc Packaged electronic device
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
US3457123A (en) * 1965-06-28 1969-07-22 Motorola Inc Methods for making semiconductor structures having glass insulated islands

Also Published As

Publication number Publication date
FR1578928A (en:Method) 1969-08-22
BE715204A (en:Method) 1968-09-30
NL6806852A (en:Method) 1968-11-18
CH472120A (fr) 1969-04-30
SE334654B (en:Method) 1971-05-03
DE1766392A1 (de) 1971-07-22
US3489952A (en) 1970-01-13
GB1165854A (en) 1969-10-01

Similar Documents

Publication Publication Date Title
ES367720A1 (es) Un metodo de montar un sistema microelectronico unitario.
US3716907A (en) Method of fabrication of semiconductor device package
CA1040747A (en) Integrated circuit package utilizing novel heat sink structure
US4143456A (en) Semiconductor device insulation method
GB1469085A (en) Semiconductor wafers
CN109616441A (zh) 半导体器件及其制造方法
GB1569453A (en) Circuit packages and methods for making circuits packages
JPH0758258A (ja) 改良された放熱能力を有する半導体デバイス
US3675089A (en) Heat dispenser from a semiconductor wafer by a multiplicity of unaligned minuscule heat conductive raised dots
JPS62230027A (ja) 半導体装置の製造方法
GB1231019A (en:Method)
US3805123A (en) Arrangement for adhesively joining heat-dissipating circuit components to heat sinks and method of making them
US3567506A (en) Method for providing a planar transistor with heat-dissipating top base and emitter contacts
UST955008I4 (en) Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate
GB1240977A (en) Improvements in or relating to semiconductor components
US3371148A (en) Semiconductor device package and method of assembly therefor
US4110598A (en) Thermal printhead assembly
GB1101906A (en) Improvements in or relating to the manufacture of semiconductor circuits or assemblies
EP0015053A1 (en) A method of manufacturing a semi-conductor power device assembly and an assembly thereby produced
JPH05109786A (ja) 半導体チツプの実装構造
GB1191093A (en) Improvement of the Electrode Lead-Out Structure of a Semiconductor Device
GB1033813A (en) Electrical semiconductor device
US7388297B2 (en) Semiconductor device with reduced thickness of the semiconductor substrate
US3447038A (en) Method and apparatus for interconnecting microelectronic circuit wafers
FR2282720B1 (en:Method)