ES2294632T3 - Metodo y dispositivo para el muestreo de datos digitales en una transmision sincronizada, conservando la integridad binaria. - Google Patents

Metodo y dispositivo para el muestreo de datos digitales en una transmision sincronizada, conservando la integridad binaria. Download PDF

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Publication number
ES2294632T3
ES2294632T3 ES05101592T ES05101592T ES2294632T3 ES 2294632 T3 ES2294632 T3 ES 2294632T3 ES 05101592 T ES05101592 T ES 05101592T ES 05101592 T ES05101592 T ES 05101592T ES 2294632 T3 ES2294632 T3 ES 2294632T3
Authority
ES
Spain
Prior art keywords
clock
hls
local
data
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES05101592T
Other languages
English (en)
Spanish (es)
Inventor
Pierre THALES Intellectual Property Courant
Christophe THALES Intellectual Property Marron
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thales SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales SA filed Critical Thales SA
Application granted granted Critical
Publication of ES2294632T3 publication Critical patent/ES2294632T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Time-Division Multiplex Systems (AREA)
ES05101592T 2004-03-05 2005-03-02 Metodo y dispositivo para el muestreo de datos digitales en una transmision sincronizada, conservando la integridad binaria. Active ES2294632T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0402351A FR2867334B1 (fr) 2004-03-05 2004-03-05 Procede et dispositif d'echantillonnage de donnees numeriques dans une transmission synchrone, avec maintien de l'integrite binaire
FR0402351 2004-03-05

Publications (1)

Publication Number Publication Date
ES2294632T3 true ES2294632T3 (es) 2008-04-01

Family

ID=34746500

Family Applications (1)

Application Number Title Priority Date Filing Date
ES05101592T Active ES2294632T3 (es) 2004-03-05 2005-03-02 Metodo y dispositivo para el muestreo de datos digitales en una transmision sincronizada, conservando la integridad binaria.

Country Status (7)

Country Link
US (2) US7509514B2 (fr)
EP (1) EP1571531B1 (fr)
AT (1) ATE375540T1 (fr)
DE (1) DE602005002766T2 (fr)
ES (1) ES2294632T3 (fr)
FR (1) FR2867334B1 (fr)
PL (1) PL1571531T3 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1737146B1 (fr) * 2005-06-22 2015-09-16 Saab Ab Système et procédé pour la transmission d'information
US7924061B2 (en) * 2006-03-27 2011-04-12 Freescale Semiconductor, Inc. Apparatus for detecting clock failure and method therefor
EP3251118A1 (fr) * 2015-01-28 2017-12-06 Dynastrom ApS Synchronisation temporelle audio à l'aide d'un programme à ordre de priorités

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972442A (en) * 1989-04-27 1990-11-20 Northern Telecom Limited Phase-locked loop clock
DE69811262T2 (de) * 1997-10-10 2003-11-27 Rambus Inc Verfahren und vorrichtung zur ausfallsicheren resynchronisation mit minimaler latenzzeit
EP0960494B1 (fr) * 1997-12-16 2006-03-08 Koninklijke Philips Electronics N.V. Synchronisation dans un systeme de transmission atm en stm
ITTO980007A1 (it) * 1998-01-07 1999-07-07 Alsthom Cge Alcatel Sistema e/o procedimento per il riconoscimento e inseguimento della fase di campionamento in sistemi di trasmissione digitale sincroni.
DE19830260A1 (de) * 1998-07-07 2000-01-13 Alcatel Sa Taktgenerator und Synchronisierungsverfahren
US6347128B1 (en) * 1998-07-20 2002-02-12 Lucent Technologies Inc. Self-aligned clock recovery circuit with proportional phase detector
US6246702B1 (en) * 1998-08-19 2001-06-12 Path 1 Network Technologies, Inc. Methods and apparatus for providing quality-of-service guarantees in computer networks
EP1075107A1 (fr) * 1999-08-06 2001-02-07 STMicroelectronics S.r.l. Circuit d'interface synchrone bidirectionnel avec une base de temps unique
US6518800B2 (en) * 2000-05-31 2003-02-11 Texas Instruments Incorporated System and method for reducing timing mismatch in sample and hold circuits using the clock
AUPQ896300A0 (en) * 2000-07-24 2000-08-17 Nec Australia Pty Ltd A clock synchronisation method for usb sink devices
US6452541B1 (en) * 2001-02-20 2002-09-17 Motorola, Inc. Time synchronization of a satellite positioning system enabled mobile receiver and base station
FR2830954A1 (fr) * 2001-10-15 2003-04-18 St Microelectronics Sa Dispositif de transmission de donnees asynchrones comprenant des moyens de controle de deviation d'horloge
US7668243B2 (en) * 2004-05-18 2010-02-23 Texas Instruments Incorporated Audio and video clock synchronization in a wireless network

Also Published As

Publication number Publication date
EP1571531B1 (fr) 2007-10-10
US7509514B2 (en) 2009-03-24
US7444533B2 (en) 2008-10-28
US20050198549A1 (en) 2005-09-08
FR2867334A1 (fr) 2005-09-09
DE602005002766T2 (de) 2008-07-24
US20080144755A1 (en) 2008-06-19
ATE375540T1 (de) 2007-10-15
FR2867334B1 (fr) 2006-04-28
PL1571531T3 (pl) 2008-02-29
EP1571531A1 (fr) 2005-09-07
DE602005002766D1 (de) 2007-11-22

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