ES2185046T3 - Caja de transistores de potencia radioelectrica con doble conexion a tierra. - Google Patents

Caja de transistores de potencia radioelectrica con doble conexion a tierra.

Info

Publication number
ES2185046T3
ES2185046T3 ES97941326T ES97941326T ES2185046T3 ES 2185046 T3 ES2185046 T3 ES 2185046T3 ES 97941326 T ES97941326 T ES 97941326T ES 97941326 T ES97941326 T ES 97941326T ES 2185046 T3 ES2185046 T3 ES 2185046T3
Authority
ES
Spain
Prior art keywords
ceramic substrate
grounding path
metallic
transistor
box
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES97941326T
Other languages
English (en)
Inventor
Thomas W Moller
Larry Leighton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson Inc
Original Assignee
Ericsson Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Inc filed Critical Ericsson Inc
Application granted granted Critical
Publication of ES2185046T3 publication Critical patent/ES2185046T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

UN CUBIERTA DE TRANSISTOR DE POTENCIA DE RF (10) CONFIGURADA PARA MONTARLA EN EL DISIPADOR TERMICO DE UN TABLERO DE CIRCUITOS IMPRESOS DE MULTIPLES CAPAS Y QUE COMPRENDE UNA TRAYECTORIA DE PUESTA A TIERRA ELECTRICA LATERAL SUPERIOR DESDE UNA PASTILLA DE TRANSISTOR (16) QUE HAY COLOCADA ENCIMA DE UN SUBSTRATO CERAMICO (18) HASTA UNA BRIDA DE MONTAJE (30), SIN PASAR A TRAVES DEL SUBSTRATO CERAMICO, EJ, COLOCANDO UN REVESTIMIENTO METALICO SOBRE UNA SUPERFICIE EXTERIOR DEL SUBSTRATO CERAMICO PARA CONECTAR ELECTRICAMENTE UN HILO METALICO MONTADO EN LA PARTE SUPERIOR A LA BRIDA. TAMBIEN SE PUEDE FORMAR UNA TRAYECTORIA DE PUESTA A TIERRA DIRECTA DE LA PASTILLA DE TRANSISTOR A LA BRIDA DE MONTAJE A TRAVES DE UNOS AGUJEROS METALIZADOS (34) FORMADOS A TRAVES DEL SUBSTRATO CERAMICO. LA TRAYECTORIA DE PUESTA A TIERRA LATERAL SUPERIOR TAMBIEN ESTA CONFIGURADA PARA CONECTAR LA CAPA DE REFERENCIA DE PUESTA A TIERRA INTERMEDIA DEL TABLERO DE CIRCUITOS IMPRESOS DE MULTIPLES CAPAS CUANDO SE ASEGURA LA BRIDADE MONTAJE AL DISIPADOR TERMICO. DE ESTE MODO, LA CUBIERTA DE TRANSISTOR DE POTENCIA SE PONE A TIERRA AL MISMO POTENCIAL DE REFERENCIA QUE EL RESTO DE LOS ELEMENTOS ACOPLADOS AL TABLERO DE CIRCUITOS IMPRESOS, AL TIEMPO QUE SE MANTIENEN LAS CARACTERISTICAS DE ALTO RENDIMIENTO PROPORCIONADAS POR LOS AGUJEROS DE PUESTA A TIERRA.
ES97941326T 1996-07-19 1997-07-02 Caja de transistores de potencia radioelectrica con doble conexion a tierra. Expired - Lifetime ES2185046T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/684,474 US5889319A (en) 1996-07-19 1996-07-19 RF power package with a dual ground

Publications (1)

Publication Number Publication Date
ES2185046T3 true ES2185046T3 (es) 2003-04-16

Family

ID=24748185

Family Applications (1)

Application Number Title Priority Date Filing Date
ES97941326T Expired - Lifetime ES2185046T3 (es) 1996-07-19 1997-07-02 Caja de transistores de potencia radioelectrica con doble conexion a tierra.

Country Status (11)

Country Link
US (1) US5889319A (es)
EP (1) EP0912997B1 (es)
JP (1) JP2001502845A (es)
KR (1) KR100338655B1 (es)
CN (1) CN1230290A (es)
AU (1) AU4325997A (es)
CA (1) CA2260823A1 (es)
DE (1) DE69716081T2 (es)
ES (1) ES2185046T3 (es)
TW (1) TW358993B (es)
WO (1) WO1998003999A1 (es)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404065B1 (en) * 1998-07-31 2002-06-11 I-Xys Corporation Electrically isolated power semiconductor package
US6462413B1 (en) * 1999-07-22 2002-10-08 Polese Company, Inc. LDMOS transistor heatsink package assembly and manufacturing method
US6493861B1 (en) 1999-12-28 2002-12-10 Intel Corporation Interconnected series of plated through hole vias and method of fabrication therefor
JP2003521127A (ja) * 2000-01-28 2003-07-08 エリクソン インコーポレイテッド 多重アース信号路ｌｄｍｏｓ電力用パッケージ
US6586833B2 (en) * 2000-11-16 2003-07-01 Silicon Semiconductor Corporation Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines
US6583673B2 (en) * 2001-02-26 2003-06-24 Infineon Technologies Ag Stability enhanced multistage power amplifier
US6731002B2 (en) 2001-05-04 2004-05-04 Ixys Corporation High frequency power device with a plastic molded package and direct bonded substrate
US6727585B2 (en) 2001-05-04 2004-04-27 Ixys Corporation Power device with a plastic molded package and direct bonded substrate
US6674157B2 (en) 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
US6566749B1 (en) 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
EP2741426B1 (en) 2011-08-01 2017-12-20 Murata Manufacturing Co., Ltd. High-frequency module
US9484222B2 (en) 2014-02-19 2016-11-01 Freescale Semiconductor, Inc. Semiconductor devices, semiconductor device packages, and packaging techniques for impedance matching and/or low frequency terminations
CN106252290B (zh) * 2016-07-06 2019-03-12 苏州能讯高能半导体有限公司 封装外壳及应用该封装外壳的电子元件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3649872A (en) * 1970-07-15 1972-03-14 Trw Inc Packaging structure for high-frequency semiconductor devices
US3713006A (en) * 1971-02-08 1973-01-23 Trw Inc Hybrid transistor
DE2510982A1 (de) * 1975-03-13 1976-09-30 Bosch Gmbh Robert Hybrides halbleiterbauelement
US3958195A (en) * 1975-03-21 1976-05-18 Varian Associates R.f. transistor package having an isolated common lead
US4042952A (en) * 1976-06-09 1977-08-16 Motorola, Inc. R. F. power transistor device with controlled common lead inductance
US4193083A (en) * 1977-01-07 1980-03-11 Varian Associates, Inc. Package for push-pull semiconductor devices
US4200880A (en) * 1978-03-28 1980-04-29 Microwave Semiconductor Corp. Microwave transistor with distributed output shunt tuning
US4213141A (en) * 1978-05-12 1980-07-15 Solid State Scientific Inc. Hybrid transistor
JPS5746662A (en) * 1980-09-04 1982-03-17 Toshiba Corp Semiconductor rectifier
US4495515A (en) * 1982-07-26 1985-01-22 At&T Bell Laboratories Electrically isolating two piece mounting washer arrangement
US4574879A (en) * 1984-02-29 1986-03-11 The Bergquist Company Mounting pad for solid-state devices
JPS60210853A (ja) * 1984-03-06 1985-10-23 Fujitsu Ltd 半導体装置
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5170337A (en) * 1992-01-29 1992-12-08 General Electric Company Low-inductance package for multiple paralleled devices operating at high frequency
US5406125A (en) * 1993-04-15 1995-04-11 Martin Marietta Corp. Semiconductor device having a metalized via hole

Also Published As

Publication number Publication date
AU4325997A (en) 1998-02-10
JP2001502845A (ja) 2001-02-27
KR100338655B1 (ko) 2002-05-30
WO1998003999A1 (en) 1998-01-29
KR20010029445A (ko) 2001-04-06
EP0912997B1 (en) 2002-10-02
DE69716081T2 (de) 2003-02-06
US5889319A (en) 1999-03-30
DE69716081D1 (de) 2002-11-07
CN1230290A (zh) 1999-09-29
CA2260823A1 (en) 1998-01-29
TW358993B (en) 1999-05-21
EP0912997A1 (en) 1999-05-06

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