ES2165564T3 - Memoria cache intercalada multi-accesible, de ciclo unico. - Google Patents
Memoria cache intercalada multi-accesible, de ciclo unico.Info
- Publication number
- ES2165564T3 ES2165564T3 ES97302823T ES97302823T ES2165564T3 ES 2165564 T3 ES2165564 T3 ES 2165564T3 ES 97302823 T ES97302823 T ES 97302823T ES 97302823 T ES97302823 T ES 97302823T ES 2165564 T3 ES2165564 T3 ES 2165564T3
- Authority
- ES
- Spain
- Prior art keywords
- data section
- content
- subarrays
- cache memory
- addressable memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0851—Cache with interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
Abstract
SE PRESENTA UNA MEMORIA DE CACHE INTERCALADO QUE TIENE CAPACIDAD DE ACCESO MULTIPLE DE CICLO SIMPLE. LA MEMORIA DE CACHE INTERCALADO COMPRENDE SUBMATRICES MULTIPLES DE CELDAS DE MEMORIA, UN CIRCUITO LOGICO DE ARBITRAJE PARA RECIBIR MULTIPLES DIRECCIONES DE ENTRADA PARA AQUELLAS SUBMATRICES Y UN CIRCUITO DE ENTRADA DE DIRECCIONES PARE APLICAR LAS MULTIPLES DIRECCIONES DE ENTRADA A ESAS SUBMATRICES. CADA UNA DE LA SUBMATRICES INCLUYE UNA SECCION DE DATOS PARES Y UNA SECCION DE DATOS IMPARES Y TRES MEMORIAS DIRECCIONABLES POR EL CONTENIDO PARA RECIBIR LAS MULTIPLES DIRECCIONES DE ENTRADA PARA SU COMPARACION CON LAS ETIQUETAS ALMACENAS EN ESTAS TRES MEMORIAS DIRECCIONABLES POR EL CONTENIDO. LA PRIMERA DE LAS TRES MEMORIAS DIRECCIONABLES POR EL CONTENIDO ESTA ASOCIADA CON LA SECCION DE DATOS PARES Y LA SEGUNDA DE LAS TRES MEMORIAS DIRECCIONABLES POR EL CONTENIDO ESTA ASOCIADA CON LA SECCION DE DATOS IMPARES. EL CIRCUITO DE LOGICA DE ARBITRAJE SE UTILIZA ENTONCES PARA SELECCIONAR UNA DE LAS MULTIPLES DIRECCIONES DE ENTRADA PARA ACTUAR SI MAS DE UNA DIRECCION DE ENTRADA INTENTA ACCEDER A LA MISMA SECCION DE DATOS DE LA MISMA SUBMATRIZ.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/638,263 US5761714A (en) | 1996-04-26 | 1996-04-26 | Single-cycle multi-accessible interleaved cache |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2165564T3 true ES2165564T3 (es) | 2002-03-16 |
Family
ID=24559311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES97302823T Expired - Lifetime ES2165564T3 (es) | 1996-04-26 | 1997-04-24 | Memoria cache intercalada multi-accesible, de ciclo unico. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5761714A (es) |
EP (1) | EP0803818B1 (es) |
JP (1) | JP3468268B2 (es) |
KR (1) | KR970071281A (es) |
AT (1) | ATE211276T1 (es) |
DE (1) | DE69709226T2 (es) |
ES (1) | ES2165564T3 (es) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748595B1 (fr) * | 1996-05-10 | 1998-07-10 | Sgs Thomson Microelectronics | Memoire a acces parallele |
US5930819A (en) * | 1997-06-25 | 1999-07-27 | Sun Microsystems, Inc. | Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache |
JPH1139857A (ja) * | 1997-07-23 | 1999-02-12 | Toshiba Corp | メモリシステム及び情報処理システム |
US6226710B1 (en) | 1997-11-14 | 2001-05-01 | Utmc Microelectronic Systems Inc. | Content addressable memory (CAM) engine |
US6226707B1 (en) * | 1997-11-17 | 2001-05-01 | Siemens Aktiengesellschaft | System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line |
JPH11212864A (ja) * | 1998-01-29 | 1999-08-06 | Sanyo Electric Co Ltd | メモリ装置 |
US6240487B1 (en) * | 1998-02-18 | 2001-05-29 | International Business Machines Corporation | Integrated cache buffers |
US6202128B1 (en) * | 1998-03-11 | 2001-03-13 | International Business Machines Corporation | Method and system for pre-fetch cache interrogation using snoop port |
US6212616B1 (en) * | 1998-03-23 | 2001-04-03 | International Business Machines Corporation | Even/odd cache directory mechanism |
US6233655B1 (en) * | 1998-04-30 | 2001-05-15 | International Business Machines Corporation | Method for Quad-word Storing into 2-way interleaved L1 cache |
US6640220B1 (en) | 2000-03-14 | 2003-10-28 | Aeroflex Utmc Microelectronic Systems, Inc. | Search coprocessor subsystem having multiple search engines and dedicated key-table memory for connection to a computer system |
JP2002055879A (ja) * | 2000-08-11 | 2002-02-20 | Univ Hiroshima | マルチポートキャッシュメモリ |
US20050182884A1 (en) * | 2004-01-22 | 2005-08-18 | Hofmann Richard G. | Multiple address two channel bus structure |
TWI355588B (en) * | 2008-01-25 | 2012-01-01 | Realtek Semiconductor Corp | Arbitration device and method thereof |
US20150100733A1 (en) * | 2013-10-03 | 2015-04-09 | Synopsys, Inc. | Efficient Memory Organization |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057090B2 (ja) * | 1980-09-19 | 1985-12-13 | 株式会社日立製作所 | データ記憶装置およびそれを用いた処理装置 |
US4724518A (en) * | 1983-07-29 | 1988-02-09 | Hewlett-Packard Company | Odd/even storage in cache memory |
GB2277181B (en) * | 1991-12-23 | 1995-12-13 | Intel Corp | Interleaved cache for multiple accesses per clock in a microprocessor |
GB9205551D0 (en) * | 1992-03-13 | 1992-04-29 | Inmos Ltd | Cache memory |
US5689680A (en) * | 1993-07-15 | 1997-11-18 | Unisys Corp. | Cache memory system and method for accessing a coincident cache with a bit-sliced architecture |
US5640534A (en) * | 1994-10-05 | 1997-06-17 | International Business Machines Corporation | Method and system for concurrent access in a data cache array utilizing multiple match line selection paths |
US5805855A (en) * | 1994-10-05 | 1998-09-08 | International Business Machines Corporation | Data cache array having multiple content addressable fields per cache line |
-
1996
- 1996-04-26 US US08/638,263 patent/US5761714A/en not_active Expired - Fee Related
-
1997
- 1997-02-03 KR KR1019970003288A patent/KR970071281A/ko active IP Right Grant
- 1997-04-17 JP JP10061997A patent/JP3468268B2/ja not_active Expired - Fee Related
- 1997-04-24 ES ES97302823T patent/ES2165564T3/es not_active Expired - Lifetime
- 1997-04-24 AT AT97302823T patent/ATE211276T1/de active
- 1997-04-24 DE DE69709226T patent/DE69709226T2/de not_active Expired - Fee Related
- 1997-04-24 EP EP97302823A patent/EP0803818B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ATE211276T1 (de) | 2002-01-15 |
KR970071281A (ko) | 1997-11-07 |
US5761714A (en) | 1998-06-02 |
JP3468268B2 (ja) | 2003-11-17 |
JPH1055311A (ja) | 1998-02-24 |
EP0803818A3 (en) | 1998-04-15 |
EP0803818B1 (en) | 2001-12-19 |
EP0803818A2 (en) | 1997-10-29 |
DE69709226T2 (de) | 2002-08-22 |
DE69709226D1 (de) | 2002-01-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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