ES2146582T3 - Generador de codigo ds3 ais/reposo en paralelo. - Google Patents

Generador de codigo ds3 ais/reposo en paralelo.

Info

Publication number
ES2146582T3
ES2146582T3 ES92120813T ES92120813T ES2146582T3 ES 2146582 T3 ES2146582 T3 ES 2146582T3 ES 92120813 T ES92120813 T ES 92120813T ES 92120813 T ES92120813 T ES 92120813T ES 2146582 T3 ES2146582 T3 ES 2146582T3
Authority
ES
Spain
Prior art keywords
sts
ais
control signal
idle
idle code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92120813T
Other languages
English (en)
Inventor
William Hermas Stephenson Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Alcatel Lucent SAS
Original Assignee
Alcatel CIT SA
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA, Alcatel SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of ES2146582T3 publication Critical patent/ES2146582T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0064—Admission Control
    • H04J2203/0067—Resource management and allocation
    • H04J2203/0071—Monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Details Of Television Scanning (AREA)
  • Amplifiers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

SE PRESENTA UN APARATO PARA CONVERTIR UNA SEÑAL DIGITAL DS3 EN UN FORMATO DE MARCO DS3 EN UNA SEÑAL DIGITAL STS-1 EN UN FORMATO DE MARCO STS-1 COMO FUNCION DE UN GENERADOR DE IMPULSOS STS-1 LOCAL. UN MEDIO DE GENERACION DE CODIGO DS3 AIS/IDLE GENERA BYTES DE CODIGO DE STS-1/IDLE EN RESPUESTA A LA SEÑAL DEL GENERADOR DE IMPULSOS STS-1 LOCAL. UN CONTADOR DE BYTES DS3 CUENTA LOS BYTES DE CODIGO DS3/IDLE Y GENERANDO UNA CUENTA DE BYTES AIS/IDLE HACE POSIBLE QUE UNA SEÑAL DE CONTROL, SI EL NUMERO DE BYTES DE CODIGO DS3 AIS/IDLE ES MENOR QUE UN NUMERO PREDETERMINADO DE BYTES DS3, SEA MAPEADA EN UNA FILA DADA DEL MARCO STS-1. LOS MEDIOS DE CONTEO DE LA FILA STS-1 CUENTAN LOS IMPULSOS DE LA SEÑAL DEL GENERADOR DE SEÑALES STS-1 LOCAL Y GENERA UNA SEÑAL DE CONTROL STS-1 DISCONTINUA, QUE SE COMBINA CON LA SEÑAL DE CONTROL DE CONTEO DE BYTES AIS/IDLE REALIMENTADA PARA ACTIVAR Y DESACTIVAR EL MEDIO GENERADOR DE CODIGO DS3 AIS/IDLE PARA MAPEAR LOS BYTES DE CODIGO DS3 AIS/IDLE EN LA FILA DADA DEL MARCO STS-1. EN UNA CONFORMACION PREFERIDA EL CONTADOR DE BYTES DS3 COMPRENDE UNA PLURALIDAD DE BIESTABLES Y DE LOGICA COMBINACIONAL ASOCIADA PARA CONTAR LOS BYTES DE CODIGO DS3 AIS/IDLE Y TIENE UNA LOGICA COMBINATORIA PARA LAS ENTRADAS DE RECEPCION DE LA PLURALIDAD DE BIESTABLES PARA GENERAR UNA SEÑAL DE CONTROL DE ACTIVACION DE CUENTA DE BYTES AIS/IDLE. EL MEDIO CONTADOR DE LA FILA STS-1 TIENE UNA PLURALIDAD DE BIESTABLES Y LOGICA COMBINATORIA ASOCIADA PARA CONTAR LOS IMPULSOS DE LA SEÑAL DE GENERADOR DE IMPULSOS STS-1 LOCAL, Y TIENE LOGICA COMBINATORIA QUE RECIBE LAS ENTRADAS DE LA PLURALIDAD DE BIESTABLES PARA GENERAR UNA SEÑAL DE CONTROL DE ACTIVACION STS-1 DISCONTINUA. EL APARATO TAMBIEN TIENE MEDIOS GENERADORES DE SEÑALES DE CONTROL DE FILA PARA GENERAR UNA SEÑAL DE CONTROL DE FILA CORTA PARA EL CONTADOR DE BYTES DS3.
ES92120813T 1991-12-16 1992-12-05 Generador de codigo ds3 ais/reposo en paralelo. Expired - Lifetime ES2146582T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/807,981 US5235332A (en) 1991-12-16 1991-12-16 Parallel ds3 aid/idle code generator

Publications (1)

Publication Number Publication Date
ES2146582T3 true ES2146582T3 (es) 2000-08-16

Family

ID=25197576

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92120813T Expired - Lifetime ES2146582T3 (es) 1991-12-16 1992-12-05 Generador de codigo ds3 ais/reposo en paralelo.

Country Status (5)

Country Link
US (1) US5235332A (es)
EP (1) EP0548649B1 (es)
AT (1) ATE193406T1 (es)
DE (1) DE69231089T2 (es)
ES (1) ES2146582T3 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2078632C (en) * 1991-09-19 1997-12-30 Tatsuhiko Nakagawa Sts-1 signal processing method and device which can prevent subsequent terminal equipment from generating unnecessary alarm
JPH09284299A (ja) * 1996-04-16 1997-10-31 Toshiba Corp 通信制御方法及びその装置
JP3483103B2 (ja) * 1997-10-13 2004-01-06 富士通株式会社 通信ネットワーク間インタフェース装置及びその方法
DE10065929A1 (de) * 2000-12-27 2002-07-04 Abb Power Automation Ag Baden Datenübertragungseinheit zur Erstellung einer digitalen Cross-Connect-Verbindung
CA2452862A1 (en) * 2001-08-15 2003-02-27 Paul R. Hartmann Remote module for a communications network
US6999480B2 (en) * 2001-11-26 2006-02-14 Applied Micro Circuits Corporation Method and apparatus for improving data integrity and desynchronizer recovery time after a loss of signal
JP3704709B2 (ja) * 2002-10-02 2005-10-12 日本電気株式会社 データ再同期化装置
US7356756B1 (en) * 2004-08-20 2008-04-08 Altera Corporation Serial communications data path with optional features

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967405A (en) * 1988-12-09 1990-10-30 Transwitch Corporation System for cross-connecting high speed digital SONET signals
JPH0654901B2 (ja) * 1989-02-08 1994-07-20 富士通株式会社 フォーマット変換制御方式
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer

Also Published As

Publication number Publication date
EP0548649A2 (en) 1993-06-30
DE69231089D1 (de) 2000-06-29
DE69231089T2 (de) 2000-10-05
EP0548649B1 (en) 2000-05-24
US5235332A (en) 1993-08-10
ATE193406T1 (de) 2000-06-15
EP0548649A3 (en) 1995-02-15

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