ES2112266T3 - Aparato para controlar el acceso a un bus de datos - Google Patents
Aparato para controlar el acceso a un bus de datosInfo
- Publication number
- ES2112266T3 ES2112266T3 ES91306702T ES91306702T ES2112266T3 ES 2112266 T3 ES2112266 T3 ES 2112266T3 ES 91306702 T ES91306702 T ES 91306702T ES 91306702 T ES91306702 T ES 91306702T ES 2112266 T3 ES2112266 T3 ES 2112266T3
- Authority
- ES
- Spain
- Prior art keywords
- data bus
- processing unit
- host
- local
- computing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Selective Calling Equipment (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/576,061 US5218681A (en) | 1990-08-31 | 1990-08-31 | Apparatus for controlling access to a data bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2112266T3 true ES2112266T3 (es) | 1998-04-01 |
Family
ID=24302809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES91306702T Expired - Lifetime ES2112266T3 (es) | 1990-08-31 | 1991-07-23 | Aparato para controlar el acceso a un bus de datos |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5218681A (enExample) |
| EP (1) | EP0473277B1 (enExample) |
| JP (1) | JP3379762B2 (enExample) |
| AT (1) | ATE163484T1 (enExample) |
| DE (1) | DE69128948T2 (enExample) |
| ES (1) | ES2112266T3 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9019001D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station including a direct memory access controller and interfacing means to microchannel means |
| GB9018992D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Internal bus for work station interfacing means |
| US5333277A (en) * | 1992-01-10 | 1994-07-26 | Exportech Trading Company | Data buss interface and expansion system |
| KR100188990B1 (ko) * | 1994-09-27 | 1999-06-01 | 이리마지리 쇼우이치로 | 데이타 중계 장치 및 이것을 이용한 비디오 게임 장치 |
| US5634112A (en) * | 1994-10-14 | 1997-05-27 | Compaq Computer Corporation | Memory controller having precharge prediction based on processor and PCI bus cycles |
| US5909560A (en) * | 1995-06-06 | 1999-06-01 | National Semiconductor Corporation | Target peripheral device detection in a multi-bus system |
| US5673400A (en) * | 1995-06-06 | 1997-09-30 | National Semiconductor Corporation | Method and apparatus for identifying and controlling a target peripheral device in a multiple bus system |
| US7076584B2 (en) * | 2003-05-09 | 2006-07-11 | Freescale Semiconductor, Inc. | Method and apparatus for interconnecting portions of circuitry within a data processing system |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4777591A (en) * | 1984-01-03 | 1988-10-11 | Texas Instruments Incorporated | Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems |
| US4646232A (en) * | 1984-01-03 | 1987-02-24 | Texas Instruments Incorporated | Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system |
| ATE131641T1 (de) * | 1987-06-29 | 1995-12-15 | Digital Equipment Corp | Busadapter für digitales rechensystem |
| EP0335502A3 (en) * | 1988-03-30 | 1991-07-03 | Advanced Micro Devices, Inc. | Microcontroller and associated method |
| US5129090A (en) * | 1988-05-26 | 1992-07-07 | Ibm Corporation | System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration |
| US4935868A (en) * | 1988-11-28 | 1990-06-19 | Ncr Corporation | Multiple port bus interface controller with slave bus |
| US5083259A (en) * | 1988-12-07 | 1992-01-21 | Xycom, Inc. | Computer bus interconnection device |
| US5088028A (en) * | 1989-04-07 | 1992-02-11 | Tektronix, Inc. | Lock converting bus-to-bus interface system |
-
1990
- 1990-08-31 US US07/576,061 patent/US5218681A/en not_active Expired - Lifetime
-
1991
- 1991-07-23 AT AT91306702T patent/ATE163484T1/de active
- 1991-07-23 EP EP91306702A patent/EP0473277B1/en not_active Expired - Lifetime
- 1991-07-23 DE DE69128948T patent/DE69128948T2/de not_active Expired - Lifetime
- 1991-07-23 ES ES91306702T patent/ES2112266T3/es not_active Expired - Lifetime
- 1991-08-29 JP JP21828391A patent/JP3379762B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0473277A3 (enExample) | 1994-01-19 |
| EP0473277A2 (en) | 1992-03-04 |
| US5218681A (en) | 1993-06-08 |
| DE69128948T2 (de) | 1998-09-17 |
| JPH04332063A (ja) | 1992-11-19 |
| DE69128948D1 (de) | 1998-04-02 |
| EP0473277B1 (en) | 1998-02-25 |
| JP3379762B2 (ja) | 2003-02-24 |
| ATE163484T1 (de) | 1998-03-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG2A | Definitive protection |
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