ES2099153T3 - Modulador digital sigma-delta. - Google Patents

Modulador digital sigma-delta.

Info

Publication number
ES2099153T3
ES2099153T3 ES91870103T ES91870103T ES2099153T3 ES 2099153 T3 ES2099153 T3 ES 2099153T3 ES 91870103 T ES91870103 T ES 91870103T ES 91870103 T ES91870103 T ES 91870103T ES 2099153 T3 ES2099153 T3 ES 2099153T3
Authority
ES
Spain
Prior art keywords
delay circuit
switch
integration
digital modulator
quantifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91870103T
Other languages
English (en)
Inventor
Didier Rene Haspeslagh
Erik Moerman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Original Assignee
Alcatel Bell NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Bell NV filed Critical Alcatel Bell NV
Application granted granted Critical
Publication of ES2099153T3 publication Critical patent/ES2099153T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
    • H03M7/304—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

UN MODULADOR SIGMA-DELTA DIGITAL DE SEGUNDO ORDEN EN EL QUE SE UTILIZA UN SOLO SUMADOR (AD) PARALELO MULTIBIT EN MULTIPLEX DE DIVISION DE TIEMPO CON UN CIRCUITO DE RETARDO DE INTEGRACION (DL3) ENTRE LA SALIDA DEL SUMADOR Y EL CUANTIFICADOR DE SALIDA (TD), ACOPLANDOSE TAMBIEN EL CIRCUITO DE RETARDO DE INTEGRACION A UNA ENTRADA DEL SUMADOR A TRAVES DE UN CONMUTADOR DEL MULTIPLEXOR BIDIRECCIONAL (SW1) Y A LA OTRA ENTRADA DEL SUMADOR VIA UN CIRCUITO DE RETARDO ADICIONAL (DL4). EN UNA POSICION DEL CONMUTADOR, SE AÑADE UN PATRON DE ENTRADA A LA SALIDA DEL CIRCUITO DE RETARDO ADICIONAL Y EN LA OTRA, SE INCORPORAN SALIDAS DESDE AMBOS CIRCUITOS DE RETARDO. PARA JUSTIFICAR LA AUSENCIA DE LOS SUSTRACTORES ALIMENTADOS DESDE EL CUANTIFICADOR, SE PASAN ALGUNOS BITS EMITIDOS POR EL CIRCUITO DE RETARDO DE INTEGRACION DE FORMA INVERTIDA, TANTO AL CIRCUITO DE RETARDO ADICIONAL (INV3) COMO, DESDE LA SALIDA INVERTIDA (INV1) DEL CUANTIFICADOR FINALMENTE A TRAVES DE UN TERCER CIRCUITO DE RETARDO (DL5), AL CONMUTADOR.
ES91870103T 1991-06-28 1991-06-28 Modulador digital sigma-delta. Expired - Lifetime ES2099153T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91870103A EP0531604B1 (en) 1991-06-28 1991-06-28 Digital sigma-delta modulator

Publications (1)

Publication Number Publication Date
ES2099153T3 true ES2099153T3 (es) 1997-05-16

Family

ID=8209024

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91870103T Expired - Lifetime ES2099153T3 (es) 1991-06-28 1991-06-28 Modulador digital sigma-delta.

Country Status (8)

Country Link
US (1) US5325399A (es)
EP (1) EP0531604B1 (es)
JP (1) JPH05206958A (es)
CA (1) CA2072526C (es)
DE (1) DE69124238T2 (es)
ES (1) ES2099153T3 (es)
FI (1) FI922989A (es)
NO (1) NO922305L (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0702465A1 (fr) * 1994-09-13 1996-03-20 T.R.T. Telecommunications Radioelectriques Et Telephoniques Système de transmission et équipement de multiplexage-démultiplexage impliquant un flux d'éléments binaires pouvant être justifié
US5742246A (en) * 1996-03-22 1998-04-21 National Science Council Stabilizing mechanism for sigma-delta modulator
US5815102A (en) * 1996-06-12 1998-09-29 Audiologic, Incorporated Delta sigma pwm dac to reduce switching
EP0903862B1 (en) * 1997-09-19 2003-06-25 STMicroelectronics S.r.l. Double sampled switched capacitor low pass multirate filter of a sigma delta D/A converter
US5896056A (en) * 1997-12-01 1999-04-20 Texmate, Inc. Root-mean-square converter method and circuit
JP2000022544A (ja) * 1998-07-01 2000-01-21 Mitsubishi Electric Corp Ｄ／ａ変換装置
US7046098B2 (en) * 2001-11-27 2006-05-16 Texas Instruments Incorporated All-digital frequency synthesis with capacitive re-introduction of dithered tuning information
CN101145786B (zh) * 2006-09-15 2012-02-08 普诚科技股份有限公司 使用分时结构的积分三角电路及其相关方法
US7528755B2 (en) * 2007-09-06 2009-05-05 Infineon Technologies Ag Sigma-delta modulator for operating sensors
US8615540B2 (en) * 2009-07-24 2013-12-24 Honeywell International Inc. Arithmetic logic unit for use within a flight control system
EP3681039A1 (en) 2019-01-09 2020-07-15 NXP USA, Inc. Apparatuses and methods invovling independent modulations of a digital clock signal for different frequency domains

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5382219A (en) * 1976-12-28 1978-07-20 Nec Corp Television signal coding unit
US4528551A (en) * 1979-11-28 1985-07-09 International Telephone And Telegraph Corporation Digital to analog converter employing sigma-delta modulation for use in telephone systems
JPH01233921A (ja) * 1988-03-15 1989-09-19 Toshiba Corp △−σ変調器を用いたａ／ｄ変換回路

Also Published As

Publication number Publication date
FI922989A (fi) 1992-12-29
FI922989A0 (fi) 1992-06-26
US5325399A (en) 1994-06-28
EP0531604B1 (en) 1997-01-15
NO922305D0 (no) 1992-06-11
CA2072526A1 (en) 1992-12-29
NO922305L (no) 1992-12-29
DE69124238T2 (de) 1997-07-03
EP0531604A1 (en) 1993-03-17
JPH05206958A (ja) 1993-08-13
CA2072526C (en) 1998-02-24
DE69124238D1 (de) 1997-02-27

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