ES2062112T3 - Procedimiento para la supervision de la capacidad de regulacion de un circuito regulador de fases. - Google Patents
Procedimiento para la supervision de la capacidad de regulacion de un circuito regulador de fases.Info
- Publication number
- ES2062112T3 ES2062112T3 ES90100645T ES90100645T ES2062112T3 ES 2062112 T3 ES2062112 T3 ES 2062112T3 ES 90100645 T ES90100645 T ES 90100645T ES 90100645 T ES90100645 T ES 90100645T ES 2062112 T3 ES2062112 T3 ES 2062112T3
- Authority
- ES
- Spain
- Prior art keywords
- phase
- locked loop
- control capability
- supervision
- procedure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001105 regulatory effect Effects 0.000 title 1
- 235000008694 Humulus lupulus Nutrition 0.000 abstract 1
- 230000001960 triggered effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0691—Synchronisation in a TDM node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
EL TRANSCURSO DE TIEMPO PARA LA VALORACION DE LA CAPACIDAD DE REGULACION DE UN CIRCUITO DE REGULACION DE FASES ES HASTA AHORA DEMASIADO GRANDE, POR TANTO CADA SALTO DE FRECUENCIA GRANDE SE DEJA CERRADO EN LA ENTRADA DEL DISCRIMINADOR DE FASES. POR EL NUEVO PROCEDIMIENTO SE POSIBILITA INCLUSO EN GRANDES SALTOS DE FRECUENCIA CERRADOS, EL VALORAR EN POCO TIEMPO LA CAPACIDAD DE REGULACION DEL CIRCUITO DE REGULACION DE FASES. LA VARIACION DE LA DIFERENCIA DE FASES PROVOCADA POR UN SALTO DE FRECUENCIA SE RECONOCE MEDIANTE UNOS LIMITES GRADUADOS, DE MODO QUE INCLUSO CUANDO LA DIFERENCIA DE FASES ABSOLUTA PRODUCIDA, SOBREPASA EL VALOR DE LOS LIMITES DE ALARMA, YA NO CONDUCE AL DESPRENDIMIENTO DE UNA ALARMA SINCRONIZADA. LOS LIMITES DE ALARMA PUEDEN SITUARSE MUY ABAJO O VALORARSE LA CAPACIDAD DE REGULACION DEL CIRCUITO DE REGULACION DE FASES EN POCO TIEMPO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3902831 | 1989-01-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2062112T3 true ES2062112T3 (es) | 1994-12-16 |
Family
ID=6373146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES90100645T Expired - Lifetime ES2062112T3 (es) | 1989-01-31 | 1990-01-12 | Procedimiento para la supervision de la capacidad de regulacion de un circuito regulador de fases. |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0380946B1 (es) |
JP (1) | JPH0695707B2 (es) |
AT (1) | ATE111660T1 (es) |
DE (1) | DE59007092D1 (es) |
ES (1) | ES2062112T3 (es) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2054599C (en) * | 1990-10-31 | 1996-02-20 | Nozomu Watanabe | Radio transceiver having pll synthesizer |
FR2685990A1 (fr) * | 1992-01-02 | 1993-07-09 | Sgs Thomson Microelectronics | Detecteur de verrouillage d'une boucle a verrouillage de phase. |
FI97578C (fi) * | 1994-10-14 | 1997-01-10 | Nokia Telecommunications Oy | Syntesoijan lukkiutumisen hälytyskytkentä |
CN114165298B (zh) * | 2021-11-25 | 2024-01-09 | 盛子测控科技(沈阳市)有限责任公司 | 倍频-分频联用实现转子叶片锁相跟踪定位的方法和装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59179A (ja) * | 1982-06-25 | 1984-01-05 | アドロ−ド株式会社 | 粘土 |
US4499434A (en) * | 1982-07-19 | 1985-02-12 | Rockwell International Corporation | PLL Phase error alarm related to associated receiver |
US4787097A (en) * | 1987-02-11 | 1988-11-22 | International Business Machines Corporation | NRZ phase-locked loop circuit with associated monitor and recovery circuitry |
-
1990
- 1990-01-12 AT AT90100645T patent/ATE111660T1/de not_active IP Right Cessation
- 1990-01-12 ES ES90100645T patent/ES2062112T3/es not_active Expired - Lifetime
- 1990-01-12 EP EP90100645A patent/EP0380946B1/de not_active Expired - Lifetime
- 1990-01-12 DE DE59007092T patent/DE59007092D1/de not_active Expired - Fee Related
- 1990-01-31 JP JP2019380A patent/JPH0695707B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0380946A2 (de) | 1990-08-08 |
EP0380946B1 (de) | 1994-09-14 |
JPH03196750A (ja) | 1991-08-28 |
DE59007092D1 (de) | 1994-10-20 |
EP0380946A3 (de) | 1991-04-24 |
ATE111660T1 (de) | 1994-09-15 |
JPH0695707B2 (ja) | 1994-11-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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