ES2060091T3 - Dispositivo de aceleracion de los accesos de memoria en un sistema informatico. - Google Patents

Dispositivo de aceleracion de los accesos de memoria en un sistema informatico.

Info

Publication number
ES2060091T3
ES2060091T3 ES90401028T ES90401028T ES2060091T3 ES 2060091 T3 ES2060091 T3 ES 2060091T3 ES 90401028 T ES90401028 T ES 90401028T ES 90401028 T ES90401028 T ES 90401028T ES 2060091 T3 ES2060091 T3 ES 2060091T3
Authority
ES
Spain
Prior art keywords
phase
evaluation
during
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90401028T
Other languages
English (en)
Inventor
Laurent Ducousso
Philippe Vallet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Application granted granted Critical
Publication of ES2060091T3 publication Critical patent/ES2060091T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

EL INVENTO SE SITUA EN EL CAMPO DE LOS SISTEMAS INFORMATICOS. PARA ACELERAR LOS ACCESOS A MEMORIA, SE UTILIZA UNA MEMORIA RAPIDA DE LECTURA ASOCIATIVA QUE CONTIENE UNOS EXTRACTOS FORMDOS POR UNA DIRECCION E INFORMACION ASOCIADA. CADA EXTRACTO ESTA ASOCIADO A UNA BASCULA DE REFERENCIA (BRFI) CUYO ESTADO SE MODIFICACUANDO SE UTILIZA EL EXTRACTO. EL DISPOSITIVO SEGUN EL INVENTO ESTA CONCEBIDO PARA FUNCIONAR EN DOS FASES DE RELOJ: - DURANTE UNA PRIMERA FASE (CK1), EFECTUA LA COMPARACION (HITI) ENTRE LA DIRECCION A TRADUCIR Y CADA DIRECCION CONTENIDA EN LA MEMORIA RAPIDA, EFECTUA LA EVALUACION DE UN ACONDICION DE STURACION (CL) Y BLOQUEA (CL1) EL RESULTADO DE ESTA EVALUACION; - DURANTE LA SEGUNDA FASE DE REKIH (CK2), PONE AL DIA LOS INDICADORES DE REFERENCIA (RFI) EN FUNCION DE LAS SEÑALES DE COINCIDENCIA (HITI) BLOQUEADOS DURANTE LA PRIMERA FASE (CK1) Y DE LA SEÑAL DE EVALUACION BLOQUEADA (CL1). APLICACION EN ANTEMEMORIAS Y EN LAS TRADUCCIONES DE DIRECCIONES VIRTUALES EN DIRECCIONES REALES.
ES90401028T 1989-04-13 1990-04-13 Dispositivo de aceleracion de los accesos de memoria en un sistema informatico. Expired - Lifetime ES2060091T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8904883A FR2645987B1 (fr) 1989-04-13 1989-04-13 Dispositif d'acceleration des acces memoire dans un systeme informatique

Publications (1)

Publication Number Publication Date
ES2060091T3 true ES2060091T3 (es) 1994-11-16

Family

ID=9380677

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90401028T Expired - Lifetime ES2060091T3 (es) 1989-04-13 1990-04-13 Dispositivo de aceleracion de los accesos de memoria en un sistema informatico.

Country Status (6)

Country Link
US (1) US5295253A (es)
EP (1) EP0394115B1 (es)
JP (1) JPH0362243A (es)
DE (1) DE69010549T2 (es)
ES (1) ES2060091T3 (es)
FR (1) FR2645987B1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
US5787465A (en) * 1994-07-01 1998-07-28 Digital Equipment Corporation Destination indexed miss status holding registers
US5594886A (en) * 1994-10-23 1997-01-14 Lsi Logic Corporation Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
US5987584A (en) * 1996-09-17 1999-11-16 Vlsi Technology, Inc. Wavetable address cache to reduce accesses over a PCI bus
JP3196107B2 (ja) * 1997-03-27 2001-08-06 日本電気エンジニアリング株式会社 データ交換システム
US6484230B1 (en) 1998-09-28 2002-11-19 International Business Machines Corporation Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction
FR2795196B1 (fr) 1999-06-21 2001-08-10 Bull Sa Processus de liberation de pages physiques pour mecanisme d'adressage virtuel
US6560675B1 (en) * 1999-12-30 2003-05-06 Unisys Corporation Method for controlling concurrent cache replace and return across an asynchronous interface
JP2006144806A (ja) 2003-04-04 2006-06-08 Toyo Tire & Rubber Co Ltd 液封入式防振装置
US11455110B1 (en) * 2021-09-08 2022-09-27 International Business Machines Corporation Data deduplication

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829840A (en) * 1972-07-24 1974-08-13 Ibm Virtual memory system
US4181937A (en) * 1976-11-10 1980-01-01 Fujitsu Limited Data processing system having an intermediate buffer memory
US4453230A (en) * 1977-12-29 1984-06-05 Tokyo Shibaura Electric Co., Ltd. Address conversion system
US4489378A (en) * 1981-06-05 1984-12-18 International Business Machines Corporation Automatic adjustment of the quantity of prefetch data in a disk cache operation
US4490782A (en) * 1981-06-05 1984-12-25 International Business Machines Corporation I/O Storage controller cache system with prefetch determined by requested record's position within data block
US4571674A (en) * 1982-09-27 1986-02-18 International Business Machines Corporation Peripheral storage system having multiple data transfer rates
US4680700A (en) * 1983-12-07 1987-07-14 International Business Machines Corporation Virtual memory address translation mechanism with combined hash address table and inverted page table
US4589092A (en) * 1983-12-12 1986-05-13 International Business Machines Corporation Data buffer having separate lock bit storage array
JPS62131353A (ja) * 1985-12-04 1987-06-13 Fujitsu Ltd ペ−ジング制御方式
US4774659A (en) * 1986-04-16 1988-09-27 Astronautics Corporation Of America Computer system employing virtual memory
US4885680A (en) * 1986-07-25 1989-12-05 International Business Machines Corporation Method and apparatus for efficiently handling temporarily cacheable data
US5119290A (en) * 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
GB8728494D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Multi-cache data storage system
US4980816A (en) * 1987-12-18 1990-12-25 Nec Corporation Translation look-aside buffer control system with multiple prioritized buffers
CA1300758C (en) * 1988-03-07 1992-05-12 Colin H. Cramm Mechanism for lock-up free cache operation with a remote address translation unit
US5134696A (en) * 1988-07-28 1992-07-28 International Business Machines Corp. Virtual lookaside facility
US5109496A (en) * 1989-09-27 1992-04-28 International Business Machines Corporation Most recently used address translation system with least recently used (LRU) replacement

Also Published As

Publication number Publication date
FR2645987A1 (fr) 1990-10-19
JPH0529946B2 (es) 1993-05-06
DE69010549T2 (de) 1995-01-05
EP0394115B1 (fr) 1994-07-13
DE69010549D1 (de) 1994-08-18
JPH0362243A (ja) 1991-03-18
US5295253A (en) 1994-03-15
FR2645987B1 (fr) 1991-06-07
EP0394115A1 (fr) 1990-10-24

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