ES2040480T3 - Multiplicador-adicionador parametrable en los cuerpos de galois y su empleo en un procesador de tratamiento de senal munerica. - Google Patents

Multiplicador-adicionador parametrable en los cuerpos de galois y su empleo en un procesador de tratamiento de senal munerica.

Info

Publication number
ES2040480T3
ES2040480T3 ES198989400762T ES89400762T ES2040480T3 ES 2040480 T3 ES2040480 T3 ES 2040480T3 ES 198989400762 T ES198989400762 T ES 198989400762T ES 89400762 T ES89400762 T ES 89400762T ES 2040480 T3 ES2040480 T3 ES 2040480T3
Authority
ES
Spain
Prior art keywords
galois
polynomy
parametrable
multiplier
bodies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198989400762T
Other languages
English (en)
Inventor
Marc Cognault
Jose Joaquim Sanchez
Dominique Brechard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of ES2040480T3 publication Critical patent/ES2040480T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

EL MULTIPLICADOR-SUMADOR EN LOS CUERPOS DE GALOIS ES PARAMETRABLE, ES DECIR SE PUEDE ESCOGER EL CUERPO DE GALOIS CG(2M) EN EL QUE SE REALIZAN LAS OPERACIONES POLINOMIALES, CON UN MAXIMO IGUAL A N, PREDETERMINADO POR EL CONCEPTOR. CONSTA DE: UN DECODIFICADOR (10) ORGANIZADO EN N CELULAS ELEMENTALES IDENTICAS QUE RECIBEN AL POLINOMIO GENERADOR G(M:0) Y QUE PROPORCIONA EL POLINOMIO GENERADOR SIN SU BIT DE PESO DEBIL G(M-1:0) Y UN POLINOMIO QUE MARCA EL GRADO DEL POLINOMIO GENERADOR (DG(M-1:0), Y UNA MATRIZ DE CALCULO (20), ORGANIZADA EN N COLUMNAS DE CELULAS ELEMENTALES IDENTICAS, QUE RECIBEN LOS POLINOMIOS A, B Y C DEL CUERPO DE GALOIS CG(2M) Y QUE PROPORCIONAN UN RESULTADO POLINOMIAL P = (A*B)MODULO G + C. EL INVENTO SE APLICA EN LOS PROCESADORES DE TRATAMIENTO DE SEÑAL NUMERICA PARA LAS CODIFICACIONES Y DECODIFICACIONES DETECTORAS Y CORRECTORAS DE ERRORES POR LOS CODIGOS BCH O RS.
ES198989400762T 1988-03-17 1989-03-17 Multiplicador-adicionador parametrable en los cuerpos de galois y su empleo en un procesador de tratamiento de senal munerica. Expired - Lifetime ES2040480T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8803431A FR2628862B1 (fr) 1988-03-17 1988-03-17 Multiplieur-additionneur parametrable dans les corps de galois, et son utilisation dans un processeur de traitement de signal numerique

Publications (1)

Publication Number Publication Date
ES2040480T3 true ES2040480T3 (es) 1993-10-16

Family

ID=9364337

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198989400762T Expired - Lifetime ES2040480T3 (es) 1988-03-17 1989-03-17 Multiplicador-adicionador parametrable en los cuerpos de galois y su empleo en un procesador de tratamiento de senal munerica.

Country Status (7)

Country Link
US (1) US5046037A (es)
EP (1) EP0333599B1 (es)
JP (1) JPH02504339A (es)
DE (1) DE68906063T2 (es)
ES (1) ES2040480T3 (es)
FR (1) FR2628862B1 (es)
WO (1) WO1989008882A1 (es)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339447A (en) * 1989-11-17 1994-08-16 Texas Instruments Incorporated Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data
US5414719A (en) * 1992-04-24 1995-05-09 Sharp Kabushiki Kaisha Operating circuit for galois field
EP0571019B1 (en) * 1992-05-19 2000-01-26 Koninklijke Philips Electronics N.V. Extended error protected communication system
US5396502A (en) * 1992-07-09 1995-03-07 Advanced Hardware Architectures, Inc. Single-stack implementation of a Reed-Solomon encoder/decoder
US5446745A (en) * 1992-10-05 1995-08-29 Mitsubishi Semiconductor America, Inc. Apparatus for correcting errors in optical disks
US5272661A (en) * 1992-12-15 1993-12-21 Comstream Corporation Finite field parallel multiplier
JP3170920B2 (ja) * 1992-12-25 2001-05-28 ソニー株式会社 エラー訂正方法及び訂正回路
US5768168A (en) * 1996-05-30 1998-06-16 Lg Semicon Co., Ltd. Universal galois field multiplier
US5931894A (en) * 1997-11-07 1999-08-03 National Science Council Power-sum circuit for finite field GF(2m)
JPH11196006A (ja) * 1997-12-26 1999-07-21 Nec Corp 並列処理シンドロ−ム計算回路及びリ−ド・ソロモン複合化回路
US6366941B1 (en) * 1998-02-03 2002-04-02 Texas Instruments Incorporated Multi-dimensional Galois field multiplier
US6199087B1 (en) 1998-06-25 2001-03-06 Hewlett-Packard Company Apparatus and method for efficient arithmetic in finite fields through alternative representation
US6178436B1 (en) 1998-07-01 2001-01-23 Hewlett-Packard Company Apparatus and method for multiplication in large finite fields
TW421756B (en) * 1998-10-01 2001-02-11 Wei Shiue Wen Arithmetic operation circuit of finite field GF(2<m>)
US6760742B1 (en) 2000-02-18 2004-07-06 Texas Instruments Incorporated Multi-dimensional galois field multiplier
DE10106085B4 (de) * 2001-02-08 2006-12-07 Systemonic Ag Verfahren und Anordnung zur Finiten Feld Multiplikation
US20030041300A1 (en) * 2001-08-23 2003-02-27 Koninklijke Philips Electronics N.V. Universal device for processing Reed-Solomon forward error-correction encoded messages
US7177891B2 (en) * 2002-10-09 2007-02-13 Analog Devices, Inc. Compact Galois field multiplier engine
US7082452B2 (en) * 2001-11-30 2006-07-25 Analog Devices, Inc. Galois field multiply/multiply-add/multiply accumulate
TW561400B (en) * 2002-04-26 2003-11-11 Silicon Integrated Sys Corp Systolic product-sum circuit in the dual-basis finite field GF(2m) or GF(2n))
US7403964B2 (en) * 2002-10-22 2008-07-22 Broadcom Corporation Galois field multiplier array for use within a finite field arithmetic unit
FR2853424B1 (fr) * 2003-04-04 2005-10-21 Atmel Corp Architecture de multiplicateurs polynomial et naturel combines
US7693928B2 (en) * 2003-04-08 2010-04-06 Analog Devices, Inc. Galois field linear transformer trellis system
US7543012B2 (en) * 2003-06-16 2009-06-02 Samsung Electronics Co., Ltd. Method and apparatus to perform squaring operation in finite field
WO2006120691A1 (en) * 2005-05-06 2006-11-16 Analog Devices Inc. Galois field arithmetic unit for error detection and correction in processors
US8176395B2 (en) * 2007-11-27 2012-05-08 Macronix International Co., Ltd. Memory module and writing and reading method thereof
US10110376B1 (en) 2016-03-28 2018-10-23 Secturion Systems, Inc. Systolic parallel Galois hash computing device
CN111752529B (zh) * 2020-06-30 2021-12-07 无锡中微亿芯有限公司 支持高效乘累加运算的可编程逻辑单元结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805037A (en) * 1972-02-22 1974-04-16 J Ellison N{40 th power galois linear gate
JPS60186942A (ja) * 1984-02-24 1985-09-24 Victor Co Of Japan Ltd デイジタル乗算回路
US4918638A (en) * 1986-10-15 1990-04-17 Matsushita Electric Industrial Co., Ltd. Multiplier in a galois field

Also Published As

Publication number Publication date
JPH02504339A (ja) 1990-12-06
DE68906063T2 (de) 1993-07-29
US5046037A (en) 1991-09-03
EP0333599A1 (fr) 1989-09-20
WO1989008882A1 (fr) 1989-09-21
DE68906063D1 (de) 1993-05-27
EP0333599B1 (fr) 1993-04-21
FR2628862A1 (fr) 1989-09-22
FR2628862B1 (fr) 1993-03-12

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