EP4226416A1 - Procédé de fabrication d'un substrat pour la croissance épitaxiale d'une couche d'un alliage iii-n à base de gallium - Google Patents
Procédé de fabrication d'un substrat pour la croissance épitaxiale d'une couche d'un alliage iii-n à base de galliumInfo
- Publication number
- EP4226416A1 EP4226416A1 EP21801584.0A EP21801584A EP4226416A1 EP 4226416 A1 EP4226416 A1 EP 4226416A1 EP 21801584 A EP21801584 A EP 21801584A EP 4226416 A1 EP4226416 A1 EP 4226416A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- sic
- semi
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 166
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 229910052733 gallium Inorganic materials 0.000 title claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 title description 2
- 239000000956 alloy Substances 0.000 title description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 139
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 136
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 46
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 35
- 229910002601 GaN Inorganic materials 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 20
- 238000000407 epitaxy Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 229910052720 vanadium Inorganic materials 0.000 claims description 6
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 6
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 3
- 230000032798 delamination Effects 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000004064 recycling Methods 0.000 claims description 2
- 229910001199 N alloy Inorganic materials 0.000 abstract description 21
- 239000010409 thin film Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 136
- 230000017525 heat dissipation Effects 0.000 description 9
- 239000002131 composite material Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
- C30B25/205—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer the substrate being of insulating material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Definitions
- the present invention relates to a method of manufacturing a substrate for the epitaxial growth of a layer of an III-N alloy based on gallium (i.e. a layer of gallium nitride (GaN), aluminum gallium nitride (AIGaN) or a layer of indium gallium nitride (InGaN)), as well as a method for producing such a layer of III-N alloy and a method for producing a high electron mobility transistor (HEMT) in such a III-N alloy layer.
- gallium i.e. a layer of gallium nitride (GaN), aluminum gallium nitride (AIGaN) or a layer of indium gallium nitride (InGaN)
- HEMT high electron mobility transistor
- III-N semiconductor materials in particular gallium nitride (GaN), aluminum gallium nitride (AIGaN) or gallium indium nitride (InGaN), appear particularly promising, especially for the formation high-power light-emitting diodes (LEDs) and high-frequency electronic devices, such as high-electron-mobility transistors (HEMTs) or other field-effect transistors (FETs).
- GaN gallium nitride
- AIGaN aluminum gallium nitride
- InGaN gallium indium nitride
- LEDs high-power light-emitting diodes
- HEMTs high-electron-mobility transistors
- FETs field-effect transistors
- III-N alloys are difficult to find in the form of large bulk substrates, they are generally formed by heteroepitaxy, i.e. by epitaxy on a substrate made of a different material.
- the choice of such a substrate takes into account in particular the difference in lattice parameter and the difference in thermal expansion coefficient between the material of the substrate and the III-N alloy. Indeed, the greater these differences, the greater the risks of formation in the III-N alloy layer of crystalline defects, such as dislocations, and the generation of significant mechanical stresses, likely to cause excessive deformations.
- III-N alloys The materials most frequently considered for the heteroepitaxy of III-N alloys are sapphire and silicon carbide (SiC).
- silicon carbide is particularly preferred for high-power electronic applications due to its thermal conductivity which is significantly higher than that of sapphire and which therefore makes it possible to dissipate more easily the thermal energy generated during the operation of the components.
- the aim is to use semi-insulating silicon carbide, i.e. typically having an electrical resistivity greater than or equal to 10 5 Q.cm, in order to minimize parasitic losses (generally called losses RF) in the substrate.
- this material is particularly expensive and is currently found only in the form of substrates of limited size.
- Silicon would drastically reduce manufacturing costs and provide access to large-size substrates, but structures of the III-N alloy type on silicon are penalized by RF propagation losses beyond 20 GHz and by low thermal dissipation.
- Composite structures such as SopSiC or SiCopSiC structures, have also been investigated [1] but do not prove to be entirely satisfactory. These structures respectively comprise a monocrystalline silicon layer or a monocrystalline SiC layer (intended to form a seed layer for the epitaxial growth of gallium nitride) on a polycrystalline SiC substrate.
- polycrystalline SiC is an inexpensive material, available in the form of large size substrates and providing good heat dissipation, these composite structures are penalized by the presence of a layer of silicon oxide at the interface between the single crystal silicon or SiC layer and the polycrystalline SiC substrate, which forms a thermal barrier impeding heat dissipation from the III-N alloy layer to the polycrystalline SiC substrate.
- An object of the invention is therefore to remedy the aforementioned drawbacks and in particular the limitations related to the size and cost of semi-insulating SiC substrates.
- the object of the invention is therefore to design a process for the manufacture of a substrate for the epitaxial growth of an III-N alloy based on gallium, in particular with a view to the formation of HEMT transistors or other electronic devices with high frequency and high power in which RF losses are minimized and heat dissipation is maximized.
- the invention proposes a process for manufacturing a substrate for the epitaxial growth of a layer of gallium nitride (GaN), of gallium nitride and aluminum (AIGaN) or of gallium nitride and indium (InGaN), comprising the following successive steps:
- high frequency is meant in the present text a frequency greater than 3 kHz.
- high power is meant in the present text a power greater than 0.5 W/mm injected at the gate of the transistor.
- high electrical resistivity is meant in the present text an electrical resistivity greater than or equal to 100 Q.cm.
- Si-insulating SiC silicon carbide having an electrical resistivity greater than or equal to 10 5 ⁇ .cm.
- This method makes it possible to form a substrate based on silicon or another material of high electrical resistivity at low cost and available in large dimensions, comprising a layer of semi-insulating SiC having a crystalline quality suitable for the subsequent epitaxial growth of a layer of III-N alloy and making the final structure benefit from its good heat dissipation and RF loss limitation properties. Since the semi-insulating SiC layer is in direct contact with the silicon substrate (or other material of high electrical resistivity), the structure also contains no thermal barrier.
- a process which would consist in forming the layer of semi-insulating SiC by epitaxy directly on a silicon substrate of high electrical resistivity would lead to the formation of a large number of dislocations in the semi-insulating SiC due to the difference in lattice parameter between the silicon and silicon carbide.
- the method according to the invention makes it possible to use as a seed for the growth of semi-insulating SiC a layer of monocrystalline SiC of optimal quality because it is obtained by transfer of the donor substrate.
- the use of the first receiving substrate which fulfills the function of temporary support, makes it possible to orient the silicon face of the SiC in an optimal manner in the different stages of the process.
- the first receiver substrate and the donor substrate have a difference in coefficient of thermal expansion less than or equal to 3 ⁇ 10′ 6 K′ 1 ;
- the first receiver substrate is an SiC substrate having a crystalline quality lower than that of the donor substrate;
- the thin layer of single-crystal SiC transferred onto the first receiving substrate has a thickness of less than 1 ⁇ m
- the bonding layer is formed from a thermally stable material during the epitaxial growth of the semi-insulating SiC layer and capable of being removed from the interface between the transferred monocrystalline SiC layer and the first receiving substrate;
- the bonding layer is a layer of silicon nitride or gallium nitride
- the removal of at least part of the bonding layer comprises chemical etching, laser delamination and/or the application of mechanical stress;
- the layer of semi-insulating SiC is formed by doping with vanadium during the epitaxial growth of SiC;
- the semi-insulating SiC layer is formed by simultaneous deposition of silicon, carbon and vanadium;
- the second receiver substrate is a silicon substrate having an electrical resistivity greater than or equal to 100 Q.cm;
- the epitaxial layer of semi-insulating SiC has a thickness of between 1 and 5 ⁇ m;
- the second receiver substrate is a polycrystalline SiC substrate or a polycrystalline AlN substrate having an electrical resistivity greater than or equal to 100 Q.cm;
- the epitaxial layer of semi-insulating SiC has a thickness less than or equal to 80 ⁇ m;
- the method further comprises a step of recycling the portion of the donor substrate detached from the transferred layer, with a view to forming a new donor substrate;
- the implantation of the ionic species is carried out through the silicon face of the donor substrate, and the silicon face of the donor substrate is bonded to the first receiver substrate, so that, after removal of the thin layer of monocrystalline SiC transferred, the silicon face of the semi-insulating SiC layer is exposed.
- Another object of the invention relates to a process for manufacturing a layer of a gallium-based III-N alloy on a substrate obtained by the process which has just been described.
- Said method comprises:
- the gallium nitride layer has a thickness of between 1 and 2 ⁇ m.
- Another object of the invention relates to a method of manufacturing a high electron mobility transistor (HEMT) in such a layer of III-N alloy.
- HEMT high electron mobility transistor
- Said method comprises:
- Figure 1 is a schematic cross-sectional view of a single-crystal SiC donor substrate
- FIG. 2 is a schematic sectional view of the donor substrate of FIG. 1 in which an embrittlement zone is formed by implantation of ionic species to delimit a thin layer to be transferred;
- Figure 3 is a schematic sectional view of a temporary support covered with a removable bonding layer
- Figure 4 is a schematic sectional view of the assembly of the temporary support of Figure 3 and the donor substrate of Figure 2 through the removable bonding layer;
- FIG. 5 is a schematic cross-sectional view of the detachment of the donor substrate along the embrittlement zone to transfer the thin layer of monocrystalline SiC onto the temporary support;
- Figure 6 is a schematic sectional view of the thin layer of monocrystalline SiC transferred to the temporary support after polishing its free surface
- FIG. 7 is a schematic sectional view of the formation by epitaxy of a layer of semi-insulating SiC on the thin layer of transferred monocrystalline SiC;
- FIG. 8 is a schematic sectional view of the assembly of the structure of FIG. 7 and of a receiver substrate via the epitaxial layer of semi-insulating SiC;
- Figure 9 is a schematic sectional view of the dismantling of the temporary support of the structure of Figure 8.
- FIG. 10 is a schematic sectional view of the receiver substrate and of the epitaxial layer of semi-insulating SiC after removal of the thin layer of monocrystalline SiC;
- FIG. 11 is a schematic sectional view of the formation by epitaxy of a GaN layer on the semi-insulating SiC layer;
- Figure 12 is a schematic sectional view of the formation of a heterojunction by epitaxy of a layer of an III-N alloy different from GaN on the GaN layer.
- the invention proposes a process for manufacturing substrates for the epitaxial growth of binary or ternary III-N alloys based on gallium.
- Said alloys include gallium nitride (GaN), aluminum gallium nitride (Al x Gai- x N, where 0 ⁇ x ⁇ 1, hereinafter abbreviated as AIGaN) and gallium nitride and indium ( InxGai -xN, where 0 ⁇ x ⁇ 1, hereinafter abbreviated as InGaN).
- the process uses a doped semiconductor monocrystalline silicon carbide (SiC) donor substrate, of which a thin layer, transferred onto a first receiver substrate, will serve as a seed for the growth of a layer of semi-insulating SiC.
- SiC semiconductor monocrystalline silicon carbide
- a layer transfer by the Smart CutTM process will be considered, but it goes without saying that any other layer transfer technique can be used, for example by spallation or laser cutting.
- a single-crystal SiC substrate having excellent crystalline quality that is to say in particular free of dislocations, is chosen.
- the donor substrate may be a bulk single crystal SiC substrate.
- the donor substrate can be a composite substrate, comprising a surface layer of monocrystalline SiC and at least one other layer of another material.
- the monocrystalline SiC layer has a thickness greater than or equal to 0.5 ⁇ m.
- crystal forms also called polytypes
- the most common are the 4H, 6H and 3C forms.
- the monocrystalline silicon carbide is chosen from the 4H and 6H polytypes, but all the polytypes can be envisaged to implement the present invention.
- such a substrate has a silicon 10-Si face and a carbon 10-C face.
- GaN epitaxy processes are mainly implemented on the silicon face of SiC. However, it is not excluded to manage to grow GaN on the carbon face of SiC.
- the orientation of the donor substrate (silicon face/carbon face) during the implementation of the process is chosen according to the face of the SiC intended for the growth of the GaN layer.
- an implantation of ionic species is implemented in the donor substrate 10, so as to form a zone of weakness 12 delimiting a thin layer 11 of monocrystalline SiC.
- the implanted species typically include hydrogen and/or helium. A person skilled in the art is able to define the energy and the implantation dose required.
- the implantation is carried out in the surface layer of monocrystalline SiC of said substrate.
- the implantation of the ionic species is carried out through the silicon 10-Si face of the donor substrate.
- this orientation of the donor substrate makes it possible to obtain, on the surface of the final substrate intended for the growth of the GaN layer, the silicon side of the SiC, which is more favorable.
- the implantation of the ionic species must be carried out through the 10-C carbon face of the donor substrate.
- the thin layer 11 of monocrystalline SiC has a thickness of less than 1 ⁇ m.
- a thickness is indeed accessible on an industrial scale with the Smart CutTM process.
- the implantation devices available in industrial manufacturing lines make it possible to achieve such an implantation depth.
- a first receiver substrate 20 is also provided.
- the main function of said first receiver substrate is to temporarily support the monocrystalline SiC layer 11 between its transfer from the donor substrate and the growth of a semi-insulating SiC layer on the monocrystalline SiC layer.
- the first receiver substrate is chosen to have a coefficient of thermal expansion substantially equal to that of SiC, so as not to induce stresses or deformations during the epitaxy of the semi-insulating SiC.
- the first receiver substrate and the donor substrate have a difference in coefficient of thermal expansion less than or equal to 3 ⁇ 10' 6 K' 1 .
- the first receiving substrate is also made of SiC so as to minimize the difference in coefficient of thermal expansion.
- the first receiver substrate 20 is an SiC substrate having a crystalline quality lower than that of the donor substrate.
- the first receiver substrate can be a polycrystalline SIC substrate, or else a monocrystalline SiC substrate but which can include dislocations of all types (unlike the monocrystalline SiC of the donor substrate which is chosen to be of excellent crystalline quality in order to ensure the quality of the GaN epitaxial layer).
- Such a substrate of lower crystalline quality has the advantage of being less expensive than a substrate of the same quality as the donor substrate, while being perfectly suited to the temporary support function.
- the donor substrate 10 comprising the thin layer 11 of monocrystalline SiC is bonded to the first receiver substrate 20.
- a bonding layer 21 is formed at the interface between said substrates.
- the bonding layer 21 is formed on the first receiver substrate 20, but, in other embodiments not illustrated, the bonding layer can be formed on the donor substrate (on the side of the thin layer 11 ), or partly on the donor substrate and partly on the first recipient substrate.
- the bonding layer is formed in a thermally stable material during the subsequent epitaxial growth of the semi-insulating SiC on the thin layer 11 .
- the epitaxy of 4H or 6H-SiC being carried out at a temperature typically higher than 1500°C, the material of the bonding layer is chosen so as not to degrade or dissociate at such a temperature.
- the material of the bonding layer is capable of being removed from the interface between the transferred single-crystal SiC layer and the first receiving substrate 20, for example by means of selective etching, optionally assisted by plasma.
- the bonding layer is a layer of silicon nitride or gallium nitride.
- the thickness of said layer is typically between 10 nm and a few hundred nanometers.
- the donor substrate is detached along the zone of weakness 12.
- the detachment can be caused by a heat treatment, a mechanical action, or a combination of these means. This detachment has the effect of transferring the thin layer 11 of monocrystalline SiC onto the first receiver substrate 20.
- the remainder 10' of the donor substrate can optionally be recycled for another use.
- the free face of the transferred monocrystalline SiC layer 11 is the carbon face 11-C (the silicon face 11-Si being on the bonding interface side).
- This face is polished, for example by chemical-mechanical polishing (CMP, acronym of the Anglo-Saxon term "Chemical Mechanical Polishing") to remove the defects linked to the implantation of the ionic species and to reduce the roughness of Layer 11.
- CMP chemical-mechanical polishing
- an epitaxial growth of a layer 30 of semi-insulating SiC is implemented on the thin layer 11 of monocrystalline SiC.
- the polytype of the semi-insulating SiC is advantageously identical to that of the SiC of the donor substrate.
- This epitaxial growth is carried out at a very high temperature, generally above 1500° C. but, as explained above, the bonding layer 21 is stable at this temperature. Moreover, given the low difference in thermal expansion coefficient between the material of the first receiving substrate and the SiC, the mechanical stresses generated in the stack are minimized.
- the SiC layer is doped with vanadium during its epitaxial growth.
- silicon, carbon and vanadium are simultaneously deposited, using suitable precursors in an epitaxy frame.
- the layer of semi-insulating SiC advantageously has a thickness greater than 1 ⁇ m, so as to contribute significantly to heat dissipation within the final structure. This thickness is higher than the thickness directly accessible by the Smart CutTM process with industrially available equipment.
- the process consisting in transferring a layer of monocrystalline SiC with a thickness of less than 1 ⁇ m then in forming a monocrystalline layer of monocrystalline SiC by epitaxy on said transferred layer makes it possible to circumvent the technical limits of the implantation equipment available industrially for the implementation of the Smart CutTM process. Furthermore, this process does not require a semi-insulating SiC donor substrate (which would be particularly expensive); Indeed, the transferred layer essentially having a seed layer function for the formation of the heat dissipation layer in semi-insulating SiC, the use of single-crystal SiC of standard electrical resistivity to form the transferred layer is sufficient.
- a second receiver substrate 40 which has a high electrical resistivity, and it is bonded to the layer 30 of semi-insulating SiC.
- the second receiver substrate can be a silicon substrate having an electrical resistivity greater than or equal to 100 Q.cm, a polycrystalline SiC substrate or a polycrystalline AlN substrate, also having an electrical resistivity greater than or equal to 100 Q. .cm.
- the thickness of the layer 30 of semi-insulating SiC may be adapted.
- the layer 30 of semi-insulating SiC will advantageously have a thickness of between 1 and 5 ⁇ m.
- the second receiver substrate is a polycrystalline SiC or polycrystalline AlN substrate, it may be advantageous to form the layer 30 of semi-insulating SiC over a much greater thickness. larger, up to 80 ⁇ m, for example of the order of 50 to 80 ⁇ m, to improve heat dissipation within the final structure.
- the bonding layer 21 is removed, so as to detach the first receiving substrate from the rest of the structure. During this removal, the layer 21 must be sufficiently damaged to allow a dissociation of the structure. Any suitable means can be used. For example, but in a non-limiting manner, the removal of the bonding layer can be achieved by chemical etching, laser delamination and/or the application of mechanical stress.
- the thin layer 11 is removed, so as to expose the layer 30 of semi-insulating SiC.
- the thin layer 11 can be removed by any appropriate means, such as chemical or mechanical etching.
- the exposed face is the silicon face of the semi-insulating SiC, which is favorable to the epitaxial growth of GaN.
- a suitable substrate for the epitaxial growth of III-N alloys was thus formed.
- a layer 50 of GaN (or, as mentioned above, of AlGaN or InGaN) is grown on the free face of the layer 30 of semi-insulating SiC.
- the thickness of layer 50 is typically between 1 and 2 ⁇ m.
- a heterojunction is formed by growing by epitaxy, on layer 50, a layer 60 of an III-N alloy different from that of layer 50.
- transistors in particular HEMT transistors, from this heterojunction, by methods known to those skilled in the art, the channel of the transistor being formed at the level of the heterojunction, and the source, the drain and the gate of the transistor being formed on the channel.
- the structure thus obtained is particularly advantageous in that it comprises a relatively thick layer of semi-insulating SiC, which on the one hand serves as a seed for the epitaxial growth of the III-N alloy layer and which on the other hand provides good heat dissipation and limitation of RF losses. Furthermore, the second receiver substrate, which supports the semi-insulating SiC layer, is directly in contact with said layer, so that the structure does not include a thermal barrier.
- a HEMT transistor or other high-frequency, high-power electronic device formed in an 11-N alloy layer epitaxially formed on such a structure exhibits minimized RF losses and maximized heat dissipation.
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Abstract
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR2010209A FR3114912B1 (fr) | 2020-10-06 | 2020-10-06 | Procédé de fabrication d’un substrat pour la croissance épitaxiale d’une couche d’un alliage III-N à base de gallium |
PCT/FR2021/051708 WO2022074317A1 (fr) | 2020-10-06 | 2021-10-04 | Procédé de fabrication d'un substrat pour la croissance épitaxiale d'une couche d'un alliage iii-n à base de gallium |
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EP4226416A1 true EP4226416A1 (fr) | 2023-08-16 |
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EP21801584.0A Pending EP4226416A1 (fr) | 2020-10-06 | 2021-10-04 | Procédé de fabrication d'un substrat pour la croissance épitaxiale d'une couche d'un alliage iii-n à base de gallium |
Country Status (8)
Country | Link |
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US (1) | US20230374701A1 (fr) |
EP (1) | EP4226416A1 (fr) |
JP (1) | JP2023544984A (fr) |
KR (1) | KR20230080475A (fr) |
CN (1) | CN116420215A (fr) |
FR (1) | FR3114912B1 (fr) |
TW (1) | TW202215503A (fr) |
WO (1) | WO2022074317A1 (fr) |
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FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
FR2877491B1 (fr) * | 2004-10-29 | 2007-01-19 | Soitec Silicon On Insulator | Structure composite a forte dissipation thermique |
US9761493B2 (en) * | 2014-01-24 | 2017-09-12 | Rutgers, The State University Of New Jersey | Thin epitaxial silicon carbide wafer fabrication |
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2020
- 2020-10-06 FR FR2010209A patent/FR3114912B1/fr active Active
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2021
- 2021-08-02 TW TW110128372A patent/TW202215503A/zh unknown
- 2021-10-04 JP JP2023518171A patent/JP2023544984A/ja active Pending
- 2021-10-04 US US18/247,859 patent/US20230374701A1/en active Pending
- 2021-10-04 WO PCT/FR2021/051708 patent/WO2022074317A1/fr unknown
- 2021-10-04 KR KR1020237015259A patent/KR20230080475A/ko unknown
- 2021-10-04 EP EP21801584.0A patent/EP4226416A1/fr active Pending
- 2021-10-04 CN CN202180065484.6A patent/CN116420215A/zh active Pending
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Publication number | Publication date |
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FR3114912A1 (fr) | 2022-04-08 |
KR20230080475A (ko) | 2023-06-07 |
JP2023544984A (ja) | 2023-10-26 |
FR3114912B1 (fr) | 2022-09-02 |
CN116420215A (zh) | 2023-07-11 |
TW202215503A (zh) | 2022-04-16 |
US20230374701A1 (en) | 2023-11-23 |
WO2022074317A1 (fr) | 2022-04-14 |
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