Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/30—Stacked capacitors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
  • H01G4/008—Selection of materials
  • H01G4/0085—Fried electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
  • H01G4/012—Form of non-self-supporting electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
  • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
  • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
  • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
  • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
  • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
  • H01G4/1245—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates containing also titanates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/224—Housing; Encapsulation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/228—Terminals
  • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
  • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
  • H01G4/385—Single unit multiple capacitors, e.g. dual capacitor in one coil
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors

Definitions

• the present invention relates to a
• Ceramic-based multilayer capacitor comprising dielectric layers and electrodes arranged therebetween.
• the electrical ceramic material is generally deformed when the capacitor voltage is applied.
• the object is at least partially solved by the multilayer capacitor disclosed in claim 1 .
• a multilayer capacitor includes a capacitor element having at least two segments.
• the segments have dielectric layers made of ceramic and electrode layers arranged in between, which are in a Layer order are arranged one above the other.
• the electrode layers comprise different electrodes, including at least first and second electrodes.
• the different electrodes for example first and second electrodes, overlap in active areas.
• the areas where no different electrodes overlap are called passive areas.
• a passive area for example, only electrodes of the same type overlap, ie only first electrodes or only second electrodes or only any other uniform type of electrodes.
• a passive area can be an area of the capacitor element in which no electrodes are arranged.
• Such an area can be, for example, an edge area that adjoins an outside of the capacitor element, since the electrodes usually do not extend over the entire width of the capacitor element.
• a plurality of segments are arranged one above the other in the stacking direction, with the outermost dielectric layers of two segments forming a connection area in which the segments are firmly connected to one another parallel to the layer planes.
• the connection area is formed, for example, by the bottom dielectric layer of an upper segment and the top dielectric layer of a lower segment.
• the two dielectric layers are firmly connected to one another, for example by sintering. Sintering the stacked segments together physically and chemically bonds the adjacent dielectric layers together. Any number of segments can be connected together. A connection area is formed between each two segments.
• connection area includes a stress relief area located in a plane parallel to the electrodes.
• the relief area occupies at least the entire passive area of the capacitor.
• connection between the segments is weakened or interrupted. Mechanical stresses in the multilayer capacitor are kept low by the relief area.
• the thickness of the segments is preferably so small that mechanical stresses in the segments do not lead to the formation of cracks in the capacitor.
• This weakening is preferably pronounced in the stacking direction, which corresponds to the field direction of the capacitor.
• the weakening can be achieved by forming a gap or by using materials with different moduli of elasticity, preferably materials with lower modulus of elasticity values.
• the weakening can be achieved by inserting a material that is harder or more brittle compared to the ceramic. In the event of a load, this material can break.
• Such mechanical stresses arise, for example, when the capacitor voltage is applied.
• mechanical stresses are to be expected between active areas and passive areas, since these are subject to different electrical loads. If no stress relief areas were provided within the capacitor, such voltages would accumulate unhindered across the entire capacitor. By weakening or interrupting the connection of the segments, in particular in the passive areas, it is avoided that the mechanical stresses add up in such a way that fractures or cracks occur in the capacitor.
• the relief area is formed as an area between the segments and parallel to the layer planes, in which the segments are not firmly connected to one another.
• the relief area is textured.
• the relief area can have at least one recess.
• a connection area is formed within this recess, in which the segments are firmly connected to one another, in particular are sintered firmly to one another.
• the relief area is designed as a gap between the segments.
• the dielectric layers of the various segments can be spaced apart from one another in the relief area.
• the dielectric layers can also rest against one another in the relief area and not be connected to one another or only partially or only with reduced adhesion.
• the gap between the segments is less than the thickness of a dielectric layer.
• the individual layer planes of a capacitor element usually each have the same layer thicknesses.
• the stress relief region comprises a material whose elastic modulus differs from the elastic modulus of the dielectric layers.
• green films in particular ceramic green films, are provided to form the dielectric layers.
• a first paste comprising an organic or inorganic material, for example, is applied, for example printed, to at least one green film, which later forms an outer dielectric layer of a segment.
• the first paste is preferably only applied to the areas where relief areas are intended.
• the second, metallic paste for an electrode material is printed onto other green films, which will later form the inner dielectric layers of a segment.
• the printing and layering can take place by the electrodes in the stack being applied alternately, slightly offset from one another, so that they can later be contacted on one side at their respective exit surfaces in a comb-like manner.
• the green sheets are arranged into a stack that is sintered.
• the first paste is formed in such a way that at the points at which the first paste is applied, sintering together of the dielectric layers is wholly or partially prevented, so that a relief area is formed here.
• the layered and pressed stack can then be divided into the individual capacitors in the case of a mass production process.
• the binder is first baked out of the separated capacitors (debinding). This is followed by the firing process (sintering).
• the ceramic powder at Temperatures preferably between 900 °C and 1200 °C and receives its final, predominantly crystalline structure.
• the individual dielectric layers combine to form a monolithic structure during the process.
• the dielectric layers of the segments arranged one above the other are also firmly connected to one another.
• the ceramic only achieves its desired dielectric behavior through this firing process.
• the firing process is followed by a cleaning step and, in at least one embodiment, the application of the external contact.
• the relief area is pronounced at least in all areas adjoining the outer sides of the capacitor element.
• the depth to which the relief region extends into the capacitor element from the outside is approximately the stacking height of the segments adjacent to the relief region or the dimension between the top and bottom electrodes in an adjacent segment.
• the adjacent segments usually each have the same stack height.
• the depth of the passive region on the outside of the capacitor is approximately the stack height of the adjacent segments.
• the depth to which the relief region extends into the capacitor element from the outside corresponds to twice the depth of the passive region on the outside of the capacitor.
• the depth of the relief area thus depends on the depth of the passive area.
• the relief area can include further sections that are not directly formed on the outer sides of the capacitor element. Again, the dimensions of the relief area should at least correspond to the dimensions described in the last paragraph.
• the relief area is at least partially located in an area where the different electrodes overlap.
• the relief area is therefore at least partially pronounced in an active area of the capacitor element.
• the relief area in this embodiment also includes all areas of the connection area that are arranged in a passive area of the capacitor element.
• a relief area enlarged in this way further reduces mechanical stresses between the individual segments.
• the relief area has at least a portion that does not border the outer sides of the capacitor element.
• connection area comprises a plurality of relief areas that are delimited from one another.
• connection area comprises a plurality of relief areas which are delimited from one another and which at least in part do not adjoin the outer sides of the capacitor element.
• the three last-mentioned embodiments are particularly advantageous in the case of large capacitor diameters.
• a relief area enlarged in this way or a plurality of relief areas in a connection area further reduce the mechanical stresses between the individual segments.
• the first and second electrodes at least partially overlap.
• the first and second electrodes form an active area in which an electric field acts and in which mechanical stresses are thus generated within the dielectric layers.
• the electrodes comprise one or more of copper, silver, nickel, platinum and palladium. These metals are particularly suitable because of their high electrical conductivity.
• the entire multilayer capacitor is sintered in one step as described above.
• the sintering step therefore takes place after the individual layers have been stacked.
• the sintering temperature of the ceramic used for the dielectric layers must not exceed the melting temperature of the metals used for the electrodes. This can be achieved by choosing a suitable electrode metal or ceramic.
• exit surfaces on the outside of the capacitor element on which electrodes exit the capacitor element are two separate external contacts for contacting the first and second electrodes applied.
• the external contacts are preferably applied to opposite outer surfaces of the multilayer capacitor.
• each segment comprises at least three different types of electrode layers, wherein in a first electrode layer the first and second electrodes are formed opposite one another and are spaced apart by a dielectric section, in a second electrode layer only first electrodes are formed and in a third Electrode layer only second electrodes are formed and the first electrode layers each form the outermost electrode layers of each segment in the stacking direction.
• the first and second electrodes face each other in the first electrode layer in a direction perpendicular to a stacking direction of the multilayer capacitor.
• Dielectric layers are in each case formed between the electrode layers.
• first and second electrodes each have the same electrical polarization as the adjacent external contacts, no electrical field builds up in the outer sections of the segments or between two segments.
• the electrodes of the first electrode layers are also partially adjacent to electrodes of the same electrical polarization within the segment are.
• no electric field builds up in a comparatively large area. This means that individual layers within the active area of the segments also have no electric field.
• the multilayer capacitor comprises at least one third electrode that is not contacted by any of the external contacts, the third electrode layer overlapping with the first and the second electrodes.
• Such an electrode is also referred to as a "floating" electrode.
• the multilayer capacitor comprises at least one third electrode that is not contiguous with either of the outer sides of the capacitor element.
• the multilayer capacitor and in particular each segment of the multilayer capacitor preferably has a multiplicity of first electrodes, a multiplicity of second electrodes and a multiplicity of third electrodes.
• the capacitor has at least one series connection of two capacitances.
• a first capacitance can be formed by overlapping at least one first electrode with at least one third electrode and a second capacitance by overlapping at least one second electrode with at least one third electrode.
• the multilayer capacitor comprises further electrodes which are arranged in the passive region of the capacitor and do not overlap with electrodes of a different polarity.
• Such electrodes are referred to as passive or dummy electrodes.
• Such dummy electrodes reduce mechanical stresses that typically occur between areas with electrodes and areas without electrodes within the capacitor element.
• thermomechanical and electrical resilience of the multilayer capacitor can be optimized in this way.
• the external contacts comprise a multilayer sputtered layer comprising layers consisting of chromium, nickel and at least one of silver or gold, the layers being applied to the exit faces in this order.
• the chromium layer which is applied directly to the exit surface, enables the sputtered layer to adhere well to the exit surface.
• the layer of silver or gold has a high level of conductivity and is therefore primarily used for making electrical contact between the electrodes.
• the sputter layer described allows all electrodes of one type to be electrically connected to one another and thus switched in parallel.
• the middle layer of nickel serves as a diffusion barrier.
• all of the first electrodes, which all emerge from the capacitor element at the same first surface can be electrically connected to one another via a first sputtered layer.
• all second electrodes, which all exit at a second surface can be electrically connected via a further second sputter layer or switched in parallel, so that for example the entire stack comprising all first and all second electrodes forms a single multilayer capacitor.
• the external contacts also include a fine-meshed copper grid, which is applied to the sputtered layer.
• the copper grid covers the entire sputter layer.
• the copper grid can avoid the formation of cracks in the sputtered layer or even the spattering of the sputtered layer in case of mechanical deformations of the capacitor element.
• the external contacts also include metal sheets, via which the capacitor element is contacted to the outside.
• the metal sheets are attached to the sputter layer.
• the metal sheets are attached to the sputtered layer by means of a soldered connection.
• the metal sheets are applied to the sputter layer by means of a sintered silver layer.
• the sputter layer described usually has a thickness in the nanometer range
• the silver layer has a thickness in the micrometer range.
• Such a sintered silver layer covering the entire sputtered layer holds the sputter layer together in the event of deformation of the capacitor element and, for example, prevents the sputter layer from crumbling.
• the silver layer also attaches the metal sheets to the sputter layer. This means that no further soldered connections are necessary. To do this, the silver is applied to the sputter layer and the metal sheets are placed directly on top of it.
• the silver layer is sintered at such a low pressure that a residual porosity of approximately 35% is achieved.
• Such porosity is low enough to only slightly reduce the silver's electrical and thermal conductivity. Due to its high electrical and thermal conductivity, the silver layer also enables a good electrical connection between the metal sheets and the sputter layer. In addition, however, silver with the porosity mentioned has a sufficiently high ductility to ensure thermomechanical relief.
• a sintered silver layer exhibits less material fatigue when subjected to mechanical or thermomechanical stress in comparison to, for example, soldered layers.
• the metal sheets comprise two layers of copper and an invar layer sandwiched between them.
• Copper has particularly good electrical and thermal conductivity.
• Invar is an iron-nickel alloy with approx. 1/3 nickel and 2/3 iron. This material has a particularly low coefficient of thermal expansion. In particular, the thermal expansion coefficient is close to the expansion coefficient of the ceramic. Due to the combination with copper, sufficient conductivity of the connection contacting can be guaranteed despite the low electrical conductivity of the Invar.
• iron-nickel or iron-nickel-cobalt alloys can also be used.
• copper layers for example, are rolled onto an Invar sheet.
• the outer surfaces of the copper layers can be silver plated to improve the bond between the copper and the sintered silver layer.
• the silver plating is applied by electroplating.
• the metal sheets of the external contacts include a copper layer with a meandering geometry.
• the copper layer is applied directly to the silver layer.
• the copper layer preferably has a meandering, grid-like geometry.
• the copper layer can also be silver-plated.
• the Silver plating is preferably carried out by electroplating.
• the copper layer can be sintered directly with the silver layer.
• the multilayer capacitor comprises separable capacitor elements that can be assembled and disassembled as desired at a contact surface, with the contact surface being arranged normal to the layer planes and the external contacts.
• Multilayer capacitor are built.
• the capacitor elements described can be mass produced in one size and then assembled according to requirements.
• the individual capacitor elements can be fixed, for example, by means of a sintered silver layer applied to the outer surfaces, which layer extends over the outer surfaces of all the capacitor elements and thus holds them together.
• the ceramic is an antiferroelectric dielectric.
• the dielectric layers can exhibit piezoelectric or electrostrictive behavior, so that the layers deform when a voltage is applied to the multilayer capacitor.
• the ceramic comprises a lead zirconate titanate. This usually crystallizes in a perovskite structure. In such a ceramic is it is an anti-ferroelectric dielectric which can be used advantageously in the described multilayer capacitor.
• the ceramic has the following composition, which has advantageous properties when used in the capacitor:
• the ceramics described have a low sintering temperature of between 900 °C and 1200 °C. Furthermore, the ceramic is characterized by high durability and low material fatigue.
• the ceramic has the following composition, which has similar advantageous properties when used in the capacitor:
• E is selected from the group consisting of Na, K and Ag;
• G is selected from the group consisting of Cu, Ni, Co and Mn;
• the ceramic has the following composition, which has similar advantageous properties when used in the capacitor:
• A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;
• E is selected from the group consisting of Cu and Ni;
• the ceramic comprises a sodium strontium titanate.
• a ceramic is also an anti-ferroelectric dielectric, which can advantageously be used in the described multilayer capacitor.
• the ceramic has the following composition, which has advantageous properties when used in the capacitor:
• the ceramic has the following composition, which also has advantageous properties when used in the capacitor:
• the ceramic has the following composition, which also has advantageous properties when used in the capacitor:
• the capacitor with the above properties is suitable for use as a DC link or snubber capacitor.
• a further application of the capacitor described is as a filter capacitor. Due to its high-frequency properties, interference signals can be well dampened and filtered up to the MHz range.
• the invention is based on
• FIG. 1 side view of a schematic representation of a first embodiment of the multilayer capacitor, not according to the invention, comprising first and second electrodes in one segment.
• FIG. 2 Side view of a schematic representation of a second exemplary embodiment of the multilayer capacitor comprising first and second electrodes in two segments.
• FIG. 3 Top view of a schematic representation of a second exemplary embodiment of the multilayer capacitor comprising first and second electrodes in two segments.
• FIG. 4 Side view of a schematic representation of a third exemplary embodiment of the multilayer capacitor comprising first and second electrodes in two segments.
• FIG. 5 Top view of a schematic representation of a third exemplary embodiment of the multilayer capacitor comprising first and second electrodes in two segments.
• FIG. 6 Side view of a schematic representation of a fourth exemplary embodiment of the multilayer capacitor comprising first, second and third electrodes in two segments.
• FIG. 7 plan view of a schematic representation of a fourth exemplary embodiment of the multilayer capacitor comprising first, second and third electrodes in two segments.
• FIG. 8 Side view of a schematic representation of a fifth exemplary embodiment of the multilayer capacitor, comprising first and second electrodes in two segments.
• FIG. 9 Top view of a schematic representation of a fifth exemplary embodiment of the multilayer capacitor comprising first and second electrodes in two segments.
• FIG. 10 Side view of a schematic representation of a sixth exemplary embodiment of the multilayer capacitor, comprising first and second electrodes in two segments.
• FIG. 11 Top view of a schematic representation of a sixth exemplary embodiment of the multilayer capacitor, comprising first and second electrodes in two segments.
• FIG. 12 Side view of a schematic representation of a seventh embodiment of the multilayer capacitor comprising first to sixth electrodes in two segments.
• FIG. 13 Top view of a schematic representation of a seventh embodiment of the multilayer capacitor comprising first to sixth electrodes in two segments.
• FIG. 14 Side view of a schematic representation of an eighth exemplary embodiment of the multilayer capacitor comprising first and second, and fourth and fifth electrodes in two segments.
• FIG. 15 plan view of a schematic representation of an eighth exemplary embodiment of the multilayer capacitor comprising first and second, and fourth and fifth electrodes in two segments.
• FIG. 16 Side view of a schematic illustration of a ninth exemplary embodiment of the multilayer capacitor, including external contacts.
• FIG. 17 Side view of a schematic representation of a metal sheet of the external contact of the ninth exemplary embodiment of the multilayer capacitor.
• FIG. 1 shows a first exemplary embodiment of the multilayer capacitor 1. The figure is essentially limited to the depiction of the capacitor element 2. Other components such as the external contacts are not shown in FIG.
• the capacitor 1 shown is constructed analogously to an example of the multilayer capacitor according to the invention, but does not include any connection areas and stress relief areas.
• the capacitor element 2 comprises a stack comprising 3 first electrodes 3, three second electrodes 4 and dielectric layers 5 arranged between or around these electrodes.
• the layers are arranged one above the other in a defined stacking direction.
• the first electrodes 3 and second electrodes 4 emerge from the cuboid capacitor element 2 on two opposite sides. These surfaces are called the first and second exit surfaces 6/7.
• the exit surfaces 6/7 are arranged normal to the stacking direction.
• the respective associated electrodes are connected to one another via an electrically conductive external contact 8 at the exit surfaces 6/7.
• the external contacts 8 each cover a large part of the exit areas 6/7. In other exemplary embodiments, the external contacts 8 can also cover smaller parts of the exit areas 6/7 or the entire exit areas 6/7.
• first and second electrodes overlap 3/4. These areas are called active areas 9A. Only first or only second electrodes 3/4 are present on the areas bordering on the exit surfaces. These areas are called passive areas 9B.
• Areas free of electrodes adjoin the two side surfaces of the capacitor element 2 normal to the exit surfaces 6/7 and normal to the stacking direction. These areas are also called passive areas 9B (compare Figure 3).
• the overlapping electrodes 3/4 function as a capacitor. Because of the voltage between the first and second electrodes 3/4, an electric field then acts in the active region 9A of the multilayer capacitor 1.
• an electric field does not have to be present over the entire stack height in the active regions 9A either. Rather, an electric field acts only between electrodes of different electric polarization, for example in dielectric layers 5, which are arranged between first and second electrodes 3/4. A field is also built up between the inner electrodes and the outer contacts if the electrical polarization differs.
• the dielectric layers 5 of the present multilayer capacitor 1 consist of an anti-ferroelectric ceramic material. A polarization of the domains of the crystal structure of the ceramic occurs in the electric field.
• the electrodes are made of an electrically conductive material such as copper, silver, nickel, palladium or platinum.
• the polarization leads to a lattice deformation in the ceramic. Because of the lattice deformation, mechanical stresses build up within the multilayer capacitor 1 . Due to the low stack height, these mechanical stresses can be neglected in the first example.
• the ceramic material of the exemplary embodiment is a perovskite ceramic.
• a perovskite ceramic usually has anti-ferroelectric properties.
• a composition of the ceramic according to one of Claims 17 to 24 also makes it possible to achieve advantageous properties for a capacitor, such as high mechanical stability and a long service life.
• the multilayer capacitor 1 shown in FIGS. 2a and 2b essentially corresponds to the multilayer capacitor 1 of the first example.
• the capacitor in FIGS. 2 and 3 has a second segment, the segments being arranged one above the other in the stacking direction.
• a single segment of the second embodiment corresponds to the segment of the first example.
• connection region 12 comprises the same dielectric ceramic material as the dielectric layers in the segments 2A and 2B of the capacitor element 2.
• connection portion 12 includes the bottom dielectric layer of a first segment 2A and the top dielectric layer of a second segment 2B, which are stacked in the stacking direction. Within the connection area 12 there is no electrode.
• connection area there is a continuous relief area 13 along the entire outer circumference of the capacitor element 2.
• the relief area 13 is arranged between the lowermost dielectric layer of the first segment 2A and the uppermost dielectric layer of the second segment 2B.
• the depth of the relief area 13, measured from the outside of the capacitor element 2 to the innermost point in the capacitor element 2, preferably corresponds to the stacking height of a segment.
• the relief area 13 includes all passive areas 9B of the multilayer capacitor 1. That is, the relief area 13 is arranged within the connecting area 12 in parallel to all portions in the segments which only include one kind of electrodes or no electrodes. Furthermore, the relief region 13 partially extends into the active region 9A of the capacitor element 2. When viewed from the stacking direction, as shown in Figure 3, the active region 9A has the shape of a rectangle.
• the passive area 9B forms a rectangular frame surrounding the active area 9A.
• the relief area 13 forms a rectangular frame that encompasses the passive area 9B and further partially overlaps the active area 9A.
• the relief area 13 is an area in which the stacked dielectric layers 5 are not firmly or only partially connected to each other.
• ceramic green films comprising a perovskite material, are provided for forming the dielectric layers 5 .
• a first paste containing an organic material is printed onto the uppermost green film of the second segment 2B.
• a second, metallic paste is printed onto other green films in the desired areas to form the electrodes.
• the green sheets are arranged into a stack that is sintered.
• the first, organic paste is formed in such a way that at the points at which the first paste is applied, sintering together of the dielectric layers 5 is wholly or partially prevented, so that a relief region 13 is formed here.
• FIGS. 4 and 5 represent a further exemplary embodiment of the multilayer capacitor 1 according to the invention.
• the relief region 13 includes, in addition to the outer section 13A along the circumference of the capacitor element 2 , an inner section 13B which extends between the outer sides, parallel to the exit surfaces 6/7 of the capacitor element 2 .
• the width of this inner section can be varied as desired. In the present embodiment, the width of the inner section exceeds the width of the outer section.
• the inner portion of the relieving region 13 is arranged entirely in parallel with the active region 9A of the multilayer capacitor 1 .
• the relief area 13 has the shape of a rectangular frame, the long sides of which are connected by means of a crossbeam.
• the cross bar corresponds to the inner section of the relief area 13.
• the charged particles may be, for example, protons present in an outer surface of the capacitor 1 due to moisture.
• the reason for this is that an electric field can build up in the outermost dielectric layer 5A of the capacitor 1 between the uppermost second electrode 4A and a first external contact. This effect can be enhanced if the external contact, for example also covers part of the top 1A of the capacitor 1 due to an error in plotting.
• FIGS. 6 and 7 A fourth exemplary embodiment of the multilayer capacitor 1 is shown in FIGS. 6 and 7, the features of which partially correspond to those of the preceding exemplary embodiments. These features will not be explained again.
• the multilayer capacitor 1 in the fourth embodiment also includes third electrodes 14 in addition to first and second electrodes.
• the third electrodes 14 are not contacted from the outside.
• the first and second electrodes 3/4 are each arranged in the same layer plane, but are still separated by a dielectric section.
• Layer planes which include the third electrodes 14, are arranged between the layer levels, which include the first and second electrodes.
• a multilayer capacitor 1 comprising two series-connected capacitors is thus formed.
• a first capacitor 1B formed between the first and third electrodes and a second capacitor IC formed between the third and second electrodes.
• the relief area 13 is designed analogously to the third exemplary embodiment.
• the relief area 13 thus comprises an outer section along the circumference of the capacitor element 2 and an inner section.
• the entire passive area 9B of the capacitor element 2 is covered by the relief area 13 due to the additional inner section. Furthermore, the relief area 13 also extends into the outer areas of the two active areas 9A of the capacitors 1B and 1C.
• Another advantage of the fourth embodiment described is that no electric field is built up between the outermost first or second electrodes 3A/4A of each segment 2A/2B of the capacitor 1 and the adjacent external contacts, since these each have the same electric polarization. Consequently, individual layers within the active region 9A also have no electric field.
• Such charged particles can be protons, for example, which can be present on the outside of the capacitor 1 due to moisture.
• Figures 8 and 9 show a fifth example of the multilayer capacitor 1. Features common to the previous embodiments will not be described again.
• the illustrated multilayer capacitor 1 in turn comprises only first and second electrodes. However, the electrodes have different dimensions.
• first and second electrodes are formed opposite one another, which are formed by a dielectric section are spaced. These first layer levels are designed analogously to the fourth embodiment.
• the first layer levels form the first and last layer level of each segment. Since the first and second electrodes 3B, 4B each have the same electrical polarization as the adjacent external contacts, no electrical field builds up here in the outer sections of the segments 2A/2B or between the two segments.
• the electrodes 3B and 4B in contrast to the electrodes 3A and 4A, are not adjacent to electrodes of opposite electrical polarization within the capacitor 1 either. Thus, no electric field builds up in a comparatively larger area. Consequently, individual layers within the active region 9A also have no electric field.
• Another advantage of the described embodiment is that no electric field is built up between the outermost first and second electrodes 3A/4A/3B/4B of each segment 2A/2B of the capacitor 1 and the adjacent external contacts, since these each have the same electric polarization. An unwanted migration of charged particles from the outside into the interior of the capacitor 1 can thus be avoided.
• the distance between the first and second electrodes in the first layer level corresponds at least to the thickness of a dielectric layer 5 in the stacking direction.
• the spacing is preferably 1.5 to three times this thickness. In this way, for example, a current flow can be avoided directly from the first electrode 3B to the opposite second electrode 4A.
• the maximum dimension of the electrodes in the first layer level is predetermined by this distance.
• the minimum dimension of the same electrodes corresponds to the depth of the passive region 9B along the outer periphery of the capacitor.
• the depth of the electrodes preferably corresponds to at least twice this depth.
• second layer planes in which only a first electrode 3 is present
• third layer planes in which only a second electrode 4 is present.
• the respective electrodes extend almost to the opposite exit surface. The distance between an electrode and the opposite exit surface corresponds to the depth of the passive region along the perimeter of the layer planes.
• Second and third layer levels are arranged alternately one above the other. In between are the dielectric layers 5.
• connection area 12 and the relief area 13 are designed as in the previous examples.
• the relief area 13 comprises an outer frame-shaped section and an inner cross-beam-shaped section.
• the outer, passive area 9B and parts of the inner, active area 9A are covered by the relief area 13, as shown graphically in FIG.
• FIGS. 10 and 11 show a sixth exemplary embodiment of the multilayer capacitor 1.
• the individual segments are designed analogously to the fourth exemplary embodiment.
• the However, the sixth exemplary embodiment differs from the fourth exemplary embodiment in the form of the relief regions 13 .
• the sixth embodiment has a plurality of different portions 13B inside. All of these sections 13B are connected to one another or to the outer section 13A of the relief area. They are preferably designed in such a way that the mechanical stresses can be relieved evenly.
• the inner sections 13B of the relief area can be arranged parallel to one another or can cross one another. The number of sections and their shape and dimensions can be varied as desired.
• Figures 12 and 13 show a further embodiment of the multilayer capacitor 1.
• the embodiment 7 essentially corresponds to the embodiment 4. It comprises first, second and third electrodes 3, 4 and 14.
• fourth, fifth and sixth electrodes 15, 16 and 17 are also pronounced in the seventh exemplary embodiment. These are dummy electrodes that fill in the passive areas 9B without creating active areas 9A themselves.
• the fourth and fifth electrodes 15 and 16 are arranged in the outer passive area of the capacitor elements 2 . They are arranged close to the external contacts and can touch them. The fourth and fifth electrodes do not generate an electric field since they only overlap with electrodes of the same polarity. Fourth electrodes 15, which are in contact with the first external contact, only overlap with such fourth electrodes 15 or first electrodes 3.
• the sixth electrodes 17 are arranged centrally in the capacitor element 2 between the first and second electrodes 3 and 4, in the same layer planes as the first and second electrodes.
• the sixth electrodes 17 only overlap further sixth electrodes 17 and third electrodes 14. Since there is no overlapping of different electrodes of different polarity in this area, this is also a passive area 9B of the capacitor element 2.
• the sixth electrodes arranged congruently one above the other in the stacking direction.
• the distance between the dummy electrodes and the active electrodes perpendicular to the field direction corresponds to at least the thickness of a dielectric layer 5, preferably 1.5 to three times the thickness of a dielectric layer 5.
• dummy electrodes reduces mechanical stresses and mechanical distortion that typically occur between areas with electrodes and areas without electrodes.
• FIGS. 14 and 15 show an eighth exemplary embodiment of the multilayer capacitor 1, which essentially corresponds to a combination of the fifth and seventh exemplary embodiment.
• fourth and fifth electrodes 15 and 16 are provided along the outer periphery of the electrode layers in the present embodiment.
• the fourth and fifth electrodes 15 and 16 are in turn in the same layers as the first and second electrodes 3 and 4.
• the fourth and fifth electrodes 15, 16 are analogous to embodiment 7 as dummy electrodes. They each overlap only with electrodes of the same polarity.
• the distance from the fourth and fifth electrodes 15, 16 to the active electrodes preferably corresponds to 1.5 to three times the thickness of a dielectric layer 5, but at least the thickness of the dielectric layer 5, in order to prevent current flow between active electrodes and opposing dummy electrodes .
• the electrodes 15A and 16B in the respective outermost segment layers thus serve the same purpose as the electrodes 3A and 4B in the fifth embodiment, but are made with a minimum suitable depth.
• the same stencil can be used each time for printing the electrode layers.
• FIG. 16 shows a ninth exemplary embodiment of the multilayer capacitor 1.
• the capacitor element 2 can be designed in accordance with one of the previous examples.
• External contacts 8 are also applied to the exit surfaces of the electrodes 6 and 7 .
• the external contacts 8 include multiple layers.
• the sputter layers 8A, which cover the entire exit surfaces 6/7, are applied directly to the exit surfaces 6/7.
• the sputtered film 8A includes three layers consisting of chromium, nickel and silver.
• All of the first and all of the second electrodes can be electrically connected to one another by the described sputter layers 8A and can thus be connected in parallel.
• the metal sheets 18 for external contacting by means of sintered silver layers 19 are applied to the sputter layers 8A.
• the silver layer 19 has in the present
• Embodiment on a thickness of about 20 gm to 30 gm.
• the porosity of the silver in the layer is 35%.
• the silver layers 19 also attach the metal sheets 18 to the sputter layers 8A. Thus, no soldering connections are necessary.
• the silver is applied to the sputter layer and the metal sheets 18 are placed directly on top of it. Only after the metal sheets 18 have been placed is the silver layer 19 sintered. Due to its high electrical conductivity, the silver layer 19 also enables a good electrical connection between the metal sheets 18 and the sputter layers 8A.
• the surfaces of the metal sheets 18 are silver-plated in the present example.
• the surfaces are preferably electroplated with silver.
• An electroplated silver layer 20 is thus formed on the surface of the metal sheets 18 and is arranged between the metal sheets 18 and the silver layer 19 .
• the thickness of the electroplated silver layer 20 is between 5 ⁇ m and 10 ⁇ m.
• the metal sheets 18 of the external contacts as shown in the detailed view in FIG. 17, comprise two copper layers 18B and an Invar layer 18A arranged between them.
• the middle layer can also comprise another iron-nickel or iron-nickel-cobalt alloy.
• the metal sheet 18 has the required mechanical strength due to the central Invar layer. Due to the low thermal expansion of the invar, a build-up of mechanical stress during temperature changes can be avoided. Crack formation in the external contact or the ceramic of the capacitor can thus be largely prevented.
• Copper layers 18B are applied to the outside of the invar layer 18A, preferably rolled on.
• the copper layers 18B have high thermal conductivity and high electrical conductivity.
• an external contact can be provided which on the one hand has a low thermal expansion coefficient and thus high mechanical stability and on the other hand has high thermal and electrical conductivity.
• the copper layers 18B are applied in an equal layer thickness on both sides of the invar layer 18A. Applying the copper evenly to both sides avoids the formation of a bimetallic strip with properties that are unfavorable for this application.
• the ratio of the layer thicknesses for copper-invar-copper is preferably 1:3:1. In the present example, a metal sheet with a total thickness of 0.15 mm is used.
• the thickness of the Invar layer 18A is 90 ⁇ m, and that of the copper layers 18B is 30 ⁇ m each.
• the layer structure described can continue to adjust the thermal expansion coefficient, the thermomechanical resilience and thus the
• the capacitor with the above properties is suitable for use as a DC link or snubber capacitor. Because of the small parasitics, particularly the low equivalent series inductance, and the ability of the capacitor to be placed close to a semiconductor, commutation circuits can be kept small. As a result, an induced overvoltage can be well damped during the switch-off process. Due to the properties of the capacitor, it is possible in some applications to do without an additional snubber capacitor when used as a DC link capacitor.
• a further application of the capacitor described is as a filter capacitor. Due to its high-frequency properties, interference signals can also be well damped and filtered far above the operating frequency of a power converter up to the MHz range.
• a copper layer is applied to the silver layer 19 instead of the metal sheet 18 .
• the copper layer has a meandering, grid-like geometry.
• the copper layer is also silver-plated here. The silver plating is done by electroplating.
• Copper layer is sintered directly with the silver layer.
• Relief area 13A Outer portion of relief area 13B Inner portion of relief area

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