EP3903341B1 - Procede de fabrication d'un substrat pour un capteur d'image de type face avant - Google Patents
Procede de fabrication d'un substrat pour un capteur d'image de type face avant Download PDFInfo
- Publication number
- EP3903341B1 EP3903341B1 EP19848983.3A EP19848983A EP3903341B1 EP 3903341 B1 EP3903341 B1 EP 3903341B1 EP 19848983 A EP19848983 A EP 19848983A EP 3903341 B1 EP3903341 B1 EP 3903341B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- semiconductor layer
- process according
- electrically insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 112
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 38
- 150000002500 ions Chemical class 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- -1 helium ions Chemical class 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 22
- 230000005540 biological transmission Effects 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 238000005259 measurement Methods 0.000 description 8
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000012212 insulator Substances 0.000 description 6
- 241000894007 species Species 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 240000008042 Zea mays Species 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000035876 healing Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
Definitions
- the present invention relates to a method of manufacturing a substrate for a front face type image sensor.
- Structures of the semiconductor on insulator type, and in particular substrates of the silicon on insulator type are interesting substrates for the manufacture of image sensors of front face type.
- An SOI substrate has, from its rear face to its front face, a silicon support substrate having a certain doping, a layer of silicon oxide called “buried oxide layer” (often designated by the acronym BOX, from the term Anglo-Saxon “Buried OXide”), and a so-called active layer of silicon having a doping which may be different from that of the support substrate.
- a matrix array of photodiodes each defining a pixel of the image sensor is arranged in the active layer.
- the buried oxide layer is chosen to be relatively thin (that is to say having a thickness of less than 100 nm, in particular of the order of 20 to 50 nm) to fulfill the function of the dielectric of a capacitor by allowing polarization by the rear face of the pixel.
- the part of the support substrate located under the buried oxide layer is biased at an electric voltage different from that of the active layer, which makes it possible to passivate the interface between the dielectric layer and the active layer.
- the electric voltage to be applied to the part of the support substrate located under the buried oxide layer depends on the thickness of the latter. The potential difference to be applied is lower the thinner the buried oxide layer is.
- this buried oxide layer Another function of this buried oxide layer is to prevent the collection of spurious signal due to the recombination in the support substrate of unabsorbed photons during their journey in each pixel (prevention of "crosstalk", according to the agreed Anglo-Saxon term ), it being understood that the buried oxide layer may, depending on the chosen thickness, be only partially reflective and/or absorbent for the incident photons.
- a disadvantage of methods for manufacturing image sensors is their high sensitivity to contamination by metals. Both the SOI substrate itself and the pixel may indeed be exposed to metals during their manufacturing processes. This exposure results in particular in the presence of metal atoms within the active layer. However, even a low concentration of atoms metals, in particular copper atoms, can result in a prohibitive loss of performance of the image sensor. Indeed, the metal atoms are liable to interact with the electrical charges generated by the photons captured in the pixels and to degrade their collection performance.
- the surface condition of the support substrate having undergone the implantation of the ions intended to form the trapping layer is of insufficient quality to ensure good bonding performance when the buried oxide layer is very thin, which represents a significant drawback of this method, in particular in the context of the bonding of thin oxides such as those targeted for a near-infrared image sensor via the front face.
- said method comprises a heat treatment carried out at a suitable temperature to cause the development of cavities from the implanted gaseous ions, said cavities forming a layer for trapping metal atoms in the support substrate.
- said heat treatment is implemented during the epitaxial growth of the additional semiconductor layer.
- the density of cavities in the trapping layer is greater than or equal to 10 15 cavities/cm 3 .
- each semiconductor layer is a silicon layer.
- the electrically insulating layer is a layer of silicon oxide.
- the electrically insulating layer consists of a stack of dielectric and/or metallic materials.
- the electrically insulating layer has a thickness comprised between 5 and 400 nm, preferably between 30 and 150 nm.
- the gaseous ions comprise helium ions.
- the invention also relates to a method for manufacturing a front face type image sensor, comprising the manufacture of a substrate by the method as described above, the transferred semiconductor layer and the semiconductor layer additional layer together forming an active layer of said image sensor, and the formation, in said active layer, of a plurality of electrically insulating trenches to delimit a plurality of pixels.
- the Figure 1A illustrates an SOI substrate for an image sensor according to one embodiment of the invention.
- Said substrate successively comprises, from its rear face to its front face, a support substrate 1, an electrically insulating layer 2 and a semiconductor layer 3, called the active layer, intended for forming the pixels of the image sensor.
- a layer 4 for trapping metal atoms is arranged at a certain depth of the support substrate 1, not necessarily in contact with the electrically insulating layer 2.
- said layer 4 comprises cavities which have developed from gaseous ions implanted in the support substrate under the effect of a heat treatment.
- the density of cavities in said trapping layer 4 is advantageously greater than or equal to 10 15 cavities/cm 3 .
- Said cavities make it possible to capture the metal atoms present in the SOI substrate in the vicinity of the electrically insulating layer 2, which can alter the proper functioning of the sensor.
- These atoms may be present initially in the support substrate 1 and/or in the active layer 3, and diffuse into the SOI substrate under the effect of heat treatments, up to the trapping layer 4 where they are captured.
- the support substrate is advantageously a silicon substrate, in particular monocrystalline.
- the electrically insulating layer 2 may be a layer of silicon oxide, which is a conventional insulator in the field of silicon-on-insulator type substrates.
- the electrically insulating layer may consist of a stack of different dielectric and/or metallic materials, such as a so-called “ONO” stack, that is to say oxide-nitride-oxide.
- the materials constituting said stack are advantageously chosen so as to increase the reflectivity of the electrically insulating layer in the infrared, compared with a layer of silicon oxide of the same total thickness.
- a metallic layer is encapsulated between two dielectric layers which thus avoid any metallic contamination of the active layer. This avoids the generation of electrical faults at the interface between the active layer and the electrically insulating layer and recombinations between the semiconductor material of the active layer and the metallic components of the image sensor, capable of doping the active layer.
- the electrically insulating layer 2 comprises a layer 22 of silicon nitride between two layers 21, 23 of silicon oxide.
- Layer 21 which is arranged on the support substrate 1 side has a thickness of between 50 and 500 nm
- layer 23 which is arranged on the active layer 3 side has a thickness of between 5 and 50 nm
- layer 22 has a thickness of between 5 and 50 nm. thickness between 10 and 100 nm.
- Such an electrically insulating layer has the advantage of reflecting the photons transmitted through the active layer 3 more than a layer of silicon oxide of identical thickness of the substrate of the Figure 1A .
- the electrically insulating layer 2 is thin, that is to say it has a thickness of between 5 and 400 nm, preferably between 30 and 150nm. Such a layer does not form a barrier to the diffusion of metal atoms, in particular copper. It is therefore not necessary, as in the document US 2010/0090303 , to locally damage the electrically insulating layer to allow the passage of atoms.
- the active layer is advantageously monocrystalline.
- the active layer 3 is formed by stacking a first layer 3a and an additional layer 3b, the layer 3b being produced by epitaxy on the layer 3a which then serves as a seed layer.
- the materials of layers 3a and 3b advantageously have lattice parameters and similar thermal expansion coefficients which make it possible to minimize the formation of crystalline defects within layer 3b during its epitaxial growth.
- layers 3a and 3b are made of the same material, typically silicon or even silicon-germanium. Layers 3a and/or 3b can optionally be doped.
- the thickness of layer 3 is typically greater than or equal to 1 ⁇ m.
- a donor substrate 30 covered with electrically insulating layer 2 is provided.
- the electrically insulating layer may be formed by thermal oxidation of the material of the donor substrate, and/or by deposition of one or more dielectric and/or metallic layers.
- an embrittlement zone is formed in the donor substrate 30, which delimits the semiconductor layer 3a to be transferred.
- the atomic species implanted for this purpose advantageously comprise hydrogen and/or helium.
- the donor substrate 30 is bonded to the support substrate 1, the electrically insulating layer 2 being at the bonding interface.
- the donor substrate 30 is detached along the embrittlement zone 31, so as to transfer the semiconductor layer 3a onto the support substrate 1.
- gaseous ions for example helium
- gaseous ions are implanted in the support substrate 1 through the semiconductor layer 3a and the electrically insulating layer 2.
- a person skilled in the art is able to define the parameters of implantation, in particular the dose and the implantation energy to locate said gaseous ions 40 in a layer in the thickness of the support substrate 1.
- a dose of between 1E16 atoms/cm 2 and 5E17 atoms/cm 2 is adapted to obtain a density of cavities of at least 10E15 cavities/cm 3 .
- the implantation energy it is typically between a few keV and 120 keV.
- a person skilled in the art will choose the appropriate energy depending on the thicknesses of the layers to be traversed by the ions in order to locate said ions in the support substrate under the electrically insulating layer.
- a heat treatment is then implemented to develop cavities from the implanted gaseous ions, so as to form a layer for trapping metal atoms.
- this treatment involves bringing the substrate to a temperature of between 850 and 1200° C., for a period of between 30 and 180 minutes.
- This heat treatment can be implemented as a specific step of the process.
- it may be advantageous to use the thermal budget of another step of the process for example a step for finishing the SOI substrate (such as a smoothing or defect healing annealing) or the epitaxy step. implemented to grow the additional semiconductor layer 3b on the transferred layer 3a.
- the transfer of the semiconductor layer can be carried out, after the bonding of the donor substrate on the support substrate, by a thinning of the donor substrate by its face opposite to the bonding interface, for example by etching, until the desired thickness is obtained for the transferred semiconductor layer.
- the formation of the zone of weakness is not necessary in this case.
- the trapping layer is formed after the bonding of the donor substrate on the support substrate, and not before as described in the document US 2010/0090303 , makes it possible to ensure optimum quality of the surfaces to be bonded and consequently good adhesion of the two substrates, including when the electrically insulating layer is thin. Furthermore, the fact that the implantation of the gaseous ions is carried out before the epitaxy of the additional semiconductor layer makes it possible to minimize the implantation energy and to avoid damaging the active layer.
- the additional semiconductor layer 3b is grown by epitaxy on the transferred layer 3a, until the desired thickness is obtained for the active layer 3.
- the thermal budget of this epitaxy can be set useful for developing the cavities forming the trapping layer 4.
- trenches are formed through the active layer 3 into the electrically insulating layer 2, and said trenches 5 are filled with a dielectric material in order to electrically isolate the pixels from the image sensor.
- SOI substrates as shown in the figure 5 were made and the trapping layer was formed by developing the cavities from the implanted gaseous ions by bringing some of said SOI substrates to a temperature of 950° C. for 40 minutes (cf. figure 7 ).
- Said substrates were then subjected to heat treatments that SOI substrates comprising the metal atom trapping layer can undergo, in order to verify that the trapping layer is stable and remains functional even after having undergone a heat treatment providing a thermal budget high (cf. figure 8 ). It is thus considered that the thermal budget of a treatment at 1100° C. for 2 hours is a maximum thermal budget making it possible to preserve the trapping properties of the layer of cavities. This thermal budget is compatible with finishing steps and possibly epitaxy.
- the figure 7 presents images of a section of the substrate of the figure 5 by a transmission electron microscope (the image on the right being a magnification of the image on the left), after the implementation of a suitable heat treatment to develop the cavities.
- the cavities arranged in a layer 4 forming a metal atom trapping layer are observed.
- layer 4 has a thickness of 179 nm and is buried at a depth of 205 nm under the interface between support substrate 1 and electrically insulating layer 2.
- the figure 8 is a transmission electron microscope image of a section of the substrate of the figure 5 after additional heat treatment applied to the substrate compared to the images of the figure 7 , said heat treatment being carried out at a temperature ranging up to 1100° C. for a period less than or equal to 2 hours.
- a temperature ranging up to 1100° C. for a period less than or equal to 2 hours.
- cavities arranged according to the layer 4 are observed, which form a layer for trapping metal atoms.
- the figure 9 presents a measurement by secondary ion mass spectrometry (SIMS) of the concentration of copper in the substrate of the figure 5 , superimposed on an image by a transmission electron microscope of a section of said substrate.
- SIMS secondary ion mass spectrometry
- a layer of copper was deposited on the semiconductor layer 3a and a heat treatment (800° C. for 2 hours) was implemented to cause the copper atoms to diffuse within the substrate.
- This heat treatment was chosen, for demonstration purposes, to ensure, given the physical properties of copper diffusion in silicon and silicon oxide, a complete dispersion of this element in the material.
- This measurement thus reflects the capacity of the copper atoms to pass through the electrically insulating layer 2 and to be trapped by the trapping layer 4.
- the concentration of copper atoms in the layer 3a is of the order of 1, 1E11 atoms/cm 3 and around 1.8E9 atoms/cm 3 in the electrically insulating layer
- the curve shows a peak at layer 4 with a concentration of copper atoms around 2.3E13 atoms/cm 3 .
- the concentration of copper atoms under layer 4 is very low.
- the figures 10 and 11 present a SIMS measurement of the concentration of copper within a substrate of the type of that of the figure 5 respectively without and with the trapping layer 4.
- a copper layer was deposited on the rear face of the support substrate 1 and a heat treatment (800° C. for 2 hours) was implemented the copper atoms within the substrate.
- a high concentration of copper atoms is observed in the support substrate 1 under the electrically insulating layer (peak P1), and a high concentration of copper atoms in the layer transferred in the vicinity of the free surface of said layer (peak P2).
- peak P3 of concentration of copper atoms is localized at the level of the trapping layer.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Facsimile Heads (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1874134A FR3091000B1 (fr) | 2018-12-24 | 2018-12-24 | Procede de fabrication d’un substrat pour un capteur d’image de type face avant |
PCT/FR2019/053281 WO2020136344A1 (fr) | 2018-12-24 | 2019-12-23 | Procede de fabrication d'un substrat pour un capteur d'image de type face avant |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3903341A1 EP3903341A1 (fr) | 2021-11-03 |
EP3903341B1 true EP3903341B1 (fr) | 2023-01-18 |
Family
ID=67956837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19848983.3A Active EP3903341B1 (fr) | 2018-12-24 | 2019-12-23 | Procede de fabrication d'un substrat pour un capteur d'image de type face avant |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP3903341B1 (ko) |
JP (1) | JP7392243B2 (ko) |
KR (1) | KR20210104876A (ko) |
FR (1) | FR3091000B1 (ko) |
IL (1) | IL284308B2 (ko) |
SG (1) | SG11202106829WA (ko) |
TW (1) | TWI810422B (ko) |
WO (1) | WO2020136344A1 (ko) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3171322B2 (ja) * | 1997-03-11 | 2001-05-28 | 日本電気株式会社 | Soi基板およびその製造方法 |
US6548382B1 (en) | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
US6083324A (en) | 1998-02-19 | 2000-07-04 | Silicon Genesis Corporation | Gettering technique for silicon-on-insulator wafers |
JP4910275B2 (ja) | 2004-09-21 | 2012-04-04 | ソニー株式会社 | 固体撮像素子及びその製造方法 |
JP2010062452A (ja) | 2008-09-05 | 2010-03-18 | Sumco Corp | 半導体基板の製造方法 |
JP2010114409A (ja) | 2008-10-10 | 2010-05-20 | Sony Corp | Soi基板とその製造方法、固体撮像装置とその製造方法、および撮像装置 |
US8614112B2 (en) * | 2010-10-01 | 2013-12-24 | Omnivision Technologies, Inc. | Method of damage-free impurity doping for CMOS image sensors |
JP5696081B2 (ja) | 2012-03-23 | 2015-04-08 | 株式会社東芝 | 固体撮像装置 |
-
2018
- 2018-12-24 FR FR1874134A patent/FR3091000B1/fr active Active
-
2019
- 2019-12-23 JP JP2021535055A patent/JP7392243B2/ja active Active
- 2019-12-23 TW TW108147236A patent/TWI810422B/zh active
- 2019-12-23 WO PCT/FR2019/053281 patent/WO2020136344A1/fr unknown
- 2019-12-23 IL IL284308A patent/IL284308B2/en unknown
- 2019-12-23 SG SG11202106829WA patent/SG11202106829WA/en unknown
- 2019-12-23 KR KR1020217023211A patent/KR20210104876A/ko unknown
- 2019-12-23 EP EP19848983.3A patent/EP3903341B1/fr active Active
Also Published As
Publication number | Publication date |
---|---|
TW202101545A (zh) | 2021-01-01 |
TWI810422B (zh) | 2023-08-01 |
IL284308B1 (en) | 2023-11-01 |
FR3091000A1 (fr) | 2020-06-26 |
IL284308A (en) | 2021-08-31 |
JP2022515096A (ja) | 2022-02-17 |
IL284308B2 (en) | 2024-03-01 |
CN113228248A (zh) | 2021-08-06 |
JP7392243B2 (ja) | 2023-12-06 |
WO2020136344A1 (fr) | 2020-07-02 |
EP3903341A1 (fr) | 2021-11-03 |
KR20210104876A (ko) | 2021-08-25 |
SG11202106829WA (en) | 2021-07-29 |
US20220059603A1 (en) | 2022-02-24 |
FR3091000B1 (fr) | 2020-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1354346B1 (fr) | Procede de realisation d'une couche mince impliquant l'implantation d'especes gazeuses | |
EP1922752B1 (fr) | Procede de report d'une couche mince sur un support | |
FR2973158A1 (fr) | Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences | |
EP0801419A1 (fr) | Procédé d'obtention d'un film mince de matériau semiconducteur comprenant notamment des composants électroniques | |
EP3806167B1 (fr) | Procede de fabrication d'au moins une photodiode planaire contrainte en tension | |
EP3660930A1 (fr) | Procédé de fabrication d'une matrice de photodiodes à base de germanium et à faible courant d'obscurité | |
FR3055467A1 (fr) | Procede de realisation d’une couche contrainte en tension a base de germanium etain | |
FR2974240A1 (fr) | Capteur eclaire par la face arriere a isolement par jonction | |
EP2979306A1 (fr) | Procédé de fabrication d'une structure à multijonctions pour cellule photovoltaïque | |
EP3903341B1 (fr) | Procede de fabrication d'un substrat pour un capteur d'image de type face avant | |
EP3568869B1 (fr) | Substrat pour capteur d'image de type face avant et procédé de fabrication d'un tel substrat | |
EP4030467B1 (fr) | Procédé de collage direct hydrophile de substrats | |
EP4088312B1 (fr) | Procédé de fabrication d'une structure de type semi-conducteur sur isolant pour applications radiofréquences | |
FR3061803B1 (fr) | Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat | |
FR3064398A1 (fr) | Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure | |
EP2701185B1 (fr) | PROCÉDÉ DE TRANSFERT D'UN FILM D'InP | |
FR3063834A1 (fr) | Procede de fabrication d'un dispositif semi-conducteur tridimensionnel | |
WO2019243751A1 (fr) | Capteur d'image de type face avant et procede de fabrication d'un tel capteur | |
WO2024141738A1 (fr) | Procédé de fabrication d'un capteur d'image | |
WO2024084179A1 (fr) | Procede de fabrication d'une couche piezoelectrique sur un substrat | |
WO2021144534A1 (fr) | Procédé de fabrication d'un capteur d'image | |
EP2254161A2 (fr) | Photodiode a controle de charge d'interface et procede associe. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20210708 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
INTG | Intention to grant announced |
Effective date: 20220830 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602019024643 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1545151 Country of ref document: AT Kind code of ref document: T Effective date: 20230215 Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: FRENCH |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: FP |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1545151 Country of ref document: AT Kind code of ref document: T Effective date: 20230118 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230518 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230418 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230518 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230419 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602019024643 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
26N | No opposition filed |
Effective date: 20231019 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20231116 Year of fee payment: 5 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: IT Payment date: 20231110 Year of fee payment: 5 Ref country code: FR Payment date: 20231108 Year of fee payment: 5 Ref country code: DE Payment date: 20231031 Year of fee payment: 5 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20231223 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20231223 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20231231 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20230118 Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20231223 |