EP3783650A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
EP3783650A1
EP3783650A1 EP20174584.1A EP20174584A EP3783650A1 EP 3783650 A1 EP3783650 A1 EP 3783650A1 EP 20174584 A EP20174584 A EP 20174584A EP 3783650 A1 EP3783650 A1 EP 3783650A1
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EP
European Patent Office
Prior art keywords
contact structure
gate
gate contact
active region
disposed
Prior art date
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Pending
Application number
EP20174584.1A
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German (de)
English (en)
French (fr)
Inventor
Chung-Liang Chu
Yu-Ruei Chen
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United Microelectronics Corp
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United Microelectronics Corp
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Publication of EP3783650A1 publication Critical patent/EP3783650A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a slot contact structure.
  • Standard cells are composed of a set or a plurality of transistors which are connected to one another, being used to execute Boolean logic functions (such as AND, OR, XOR or XNOR) or can provide storage functions (as a flip-flop or a latch).
  • Boolean logic functions such as AND, OR, XOR or XNOR
  • storage functions such as a flip-flop or a latch.
  • the layout design of the standard cells can be various. However, it would be beneficial to the layout design and/or the electrical performance of the integrate circuits by shrinking the area occupied by the standard cell. Accordingly, the method of reducing the occupied area of the standard cell by modifying the layout design in the standard cell is important for the related industries.
  • Gate contact structures are disposed adjacent to a slot contact structure for reducing the size of the semiconductor device.
  • a semiconductor device in an embodiment of the present invention.
  • the semiconductor device includes a substrate, an insolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure.
  • the substrate includes a first active region and a second active region.
  • the first active region and the second active region are elongated in a first direction respectively.
  • the isolation structure is disposed between the first active region and the second active region.
  • the first gate structure, the second gate structure, and the first slot contact structure are elongated in a second direction respectively and disposed on the first active region, the second active region, and the isolation structure.
  • the first slot contact structure is disposed between the first gate structure and the second gate structure in the first direction.
  • the first gate contact structure is disposed on and electrically connected with the first gate structure.
  • the second gate contact structure is disposed on and electrically connected with the second gate structure.
  • the first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively, and the first gate contact structure and the second gate contact structure are disposed between the first active region and the second active region in the second direction.
  • a length of the first gate contact structure in the second direction and a length of the second gate contact structure in the second direction are less than a length of the isolation structure in the second direction.
  • etch is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained.
  • the method of etching silicon involves patterning a photoresist layer over silicon and then removing silicon from the area that is not protected by the photoresist layer. Thus, after the etching process is complete, the silicon protected by the area of the photoresist layer will remain.
  • the term “etch” may also refer to a method that does not use a photoresist, but leaves at least a portion of the material layer after the etch process is complete.
  • etching When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.
  • forming or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.
  • FIG. 1 is a top view schematic drawing illustrating a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a schematic circuit diagram of the semiconductor device in this embodiment
  • FIG. 3 is a cross-sectional diagram taken along a line A-A' in FIG. 1
  • FIG. 4 is a cross-sectional diagram taken along a line B-B' in FIG. 1
  • FIG. 5 is a cross-sectional diagram taken along a line C-C' in FIG. 1
  • a semiconductor device 101 is provided in this embodiment.
  • the semiconductor device 101 includes a substrate 10, an insolation structure IS, a first gate structure GS1, a second gate structure GS2, a first slot contact structure SC1, a first gate contact structure GC1, and a second gate contact structure GC2.
  • the substrate 10 includes a first active region A1 and a second active region A2.
  • the first active region A1 and the second active region A2 are elongated in a first direction D1 respectively.
  • the isolation structure IS is disposed between the first active region A1 and the second active region A2.
  • the first gate structure GS1, the second gate structure GS2, and the first slot contact structure SC1 are elongated in a second direction D2 respectively, and the first gate structure GS1, the second gate structure GS2, and the first slot contact structure SC1 are disposed on the first active region A1, the second active region A2, and the isolation structure IS.
  • the first slot contact structure SC1 is disposed between the first gate structure GS1 and the second gate structure GS2 in the first direction D1.
  • the first gate contact structure GC1 is disposed on and electrically connected with the first gate structure GS1.
  • the second gate contact structure GC2 is disposed on and electrically connected with the second gate structure GS2.
  • the first gate contact structure GC1 and the second gate contact structure GC2 are disposed at two opposite sides of the first slot contact structure SC1 in the first direction D1 respectively, and the first gate contact structure GC1 and the second gate contact structure GC2 are disposed between the first active region A1 and the second active region A2 in the second direction D2.
  • a length of the first gate contact structure GC1 in the second direction D2 and a length of the second gate contact structure GC2 in the second direction D2 are less than a length of the isolation structure IS in the second direction D2.
  • the substrate 10 may include a semiconductor substrate, such as a silicon substrate, an epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto.
  • the isolation structure IS may be formed of a single layer or multiple layers of insulation material, such as silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials.
  • the isolation structure IS may include a shallow trench isolation (STI) structure or other suitable isolation structures configured to define a plurality of active regions separated from one another (such as the first active region A1 and the second active region A2) in the substrate 10.
  • STI shallow trench isolation
  • the first active region A1 and the second active region A2 may respectively include a semiconductor material in the substrate 10, but not limited thereto.
  • the first active region A1 and the second active region A2 may be a fin-shaped structure extending upwards from the substrate 10 respectively, and the isolation structure IS may be disposed between the fin-shaped structures adjacent to each other.
  • the first active region A1 and the second active region A2 may be elongated in the first direction D1, and the isolation structure IS may be located between the first active region A1 and the second active region A2 in the second direction D2.
  • the first direction D1 and the second direction D2 may be substantially orthogonal to each other, but not limited thereto.
  • the first gate structure GS1 and the second gate structure GS2 may include a gate material and a gate dielectric layer (not shown in FIGs. 1-5 ) located between the gate material and the substrate 10.
  • the gate material may include a metallic material a non-metallic material (such as polysilicon), or other suitable conductive materials
  • the gate dielectric layer may include an oxide layer, such as a silicon oxide layer, or other suitable dielectric materials, such as a high dielectric constant dielectric material.
  • a spacer 30 may be formed on a sidewall of the first gate structure GS1 and a sidewall of the second gate structure GS2, and a source/drain region may be formed in the active region located between the first gate structure GS1 and the second gate structure GS2.
  • the spacer 30 may include a single layer or multiple layers of insulation material, such as silicon nitride, silicon oxynitride, silicon carbonitride, or other suitable insulation materials.
  • the source/drain region described above may include a doped region, an epitaxial structure (such as an epitaxial structure 32 shown in FIG. 4 ), or other suitable source/drain structures.
  • a silicide layer 34 may be formed on the source/drain region and a silicide layer 36 may be formed on the first gate structure GS1 and the second gate structure GS2, but not limited thereto.
  • the silicide layer 34 and the silicide layer 36 may include a conductive metal silicide material, such as cobalt-silicide, nickel-silicide, or other suitable metal silicide.
  • the silicide layer 34 may be located between the first slot contact structure SC1 and the epitaxial structure 32, and the first slot contact structure SC1 may be electrically connected with the epitaxial structure 32 via the silicide layer 34.
  • the silicide layer 36 may be disposed between the first gate contact structure GC1 and the first gate structure GS1 and disposed between the second gate contact structure GC1 and the second gate structure GS2.
  • the first gate contact structure GC1 may be electrically connected with the first gate structure GS1 via the silicide layer 36
  • the second gate contact structure GC2 may be electrically connected with the second gate structure GS2 via the silicide layer 36.
  • the first gate contact structure GC1, the second gate contact structure GC2, and the first slot contact structure SC1 may respectively include a barrier layer (not shown) and a conductive material (not shown) disposed on the barrier layer, but not limited thereto.
  • a barrier layer (not shown) and a conductive material (not shown) disposed on the barrier layer, but not limited thereto.
  • other suitable types of conductive structures may also be used in the first gate contact structure GC1, the second gate contact structure GC2, and the first slot contact structure SC1.
  • the barrier layer mentioned above may include titanium nitride, tantalum nitride, or other suitable barrier materials, and the conductive material mentioned above may include a material with relatively lower resistivity, such as copper, aluminum, and tungsten, but not limited thereto.
  • a distance between the first gate contact structure GC1 and the first slot contact structure SC1 in the first direction D1 and a distance between the second gate contact structure GC2 and the first slot contact structure SC1 in the first direction D1 may be less than or equal to 12 nanometers for reducing the area occupied by the semiconductor device 101 as much as possible. Additionally, the first gate contact structure GC1 and the second gate contact structure GC2 do not overlap the first active region A1 and the second active region A2 in a thickness direction of the substrate 10 (such as a third direction D3).
  • first gate contact structure GC1 disposed adjacent to the first slot contact structure SC1 and the second gate contact structure GC2 disposed adjacent to the first slot contact structure SC1 may be disposed above the isolation structure IS without being disposed on the active regions.
  • the semiconductor device 101 may further include a dielectric layer 40, a first opening (such as an opening V1), a second opening (such as an opening V2), an opening V3, a first conductive line (such as a conductive line L1), and a conductive line L2.
  • the dielectric layer 40 is disposed on the first gate contact structure GC1, the second gate contact structure GC2, and the first slot contact structure SC1.
  • the dielectric layer 40 may include a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials, and the conductive lines may include a conductive material with relatively lower resistivity, such as copper, aluminum, and tungsten, but not limited thereto.
  • the opening V1 may penetrate the dielectric layer 40 on the first gate contact structure GC1 and expose a part of the first gate contact structure GC1
  • the opening V2 may penetrate the dielectric layer 40 on the second gate contact structure GC2 and expose a part of the second gate contact structureGC2
  • the opening V3 may penetrate the dielectric layer 40 on the first slot contact structure SC1 and expose a part of the first slot contact structure SC1.
  • the conductive line L1 and the conductive line L2 may be disposed on the dielectric layer 40 and elongated in the first direction D1 respectively.
  • a part of the conductive line L1 may be disposed on the first gate contact structure GC1, and the conductive line L1 may be electrically connected with the first gate contact structure GC1 via the opening V1.
  • another part of the conductive line L1 may be disposed on the second gate contact structure GC2, the conductive line L1 may be electrically connected with the second gate contact structure GC2 via the opening V2, and the first gate structure GS1 may be electrically connected with the second gate structure GS2 by the first gate contact structure GC1, the conductive line L1, and the second gate contact structure GC2.
  • a part of the conductive line L2 may be disposed on the first slot contact structure SC1, and the conductive line L2 may be electrically connected with the first slot contact structure SC1 via the opening V3.
  • the conductive lines mentioned above may be partly disposed in the openings (such as the opening V1, the opening V2, and the opening V3), or connection plus (not shown) may be formed in the openings, and the conductive lines may be electrically connected with the gate contact structures or the slot contact structures by the connection plugs, but not limited thereto.
  • the semiconductor device 101 may further include two third gate structures GS3, four third gate contact structures GC3, two second slot contact structure SC2, two third slot contact structures SC3, two openings V4, two openings V5, a conductive line L3, a conductive line L4, and a plurality of dummy conductive lines DL.
  • Each of the third gate structures GS3 may be elongated in the second direction D2 and disposed on the first active region A1, the second active region A2, and the isolation structure IS.
  • the two third gate structures GS3 may be located at two ends of the semiconductor device 101 in the first direction D1, and the third gate structures GS3 may be regarded as dummy gate structures, but not limited thereto.
  • the first gate structure GS1, the second gate structure GS2, and the third gate structures GS3 may be formed concurrently by the same manufacturing process and have the same composition, the same width, and equal spacing, but not limited thereto.
  • the third gate contact structure GC3 may be partly disposed on and electrically connected with the third gate structure GS3.
  • the third gate contact structure GC3, the first gate contact structure GC1, and the second gate contact structure GC2 may be formed concurrently by the same manufacturing process, and the compositions of the first gate contact structure GC1, the second gate contact structure GC2, and the third gate contact structure GC3 may be identical to one another, but not limited thereto.
  • Each of the second slot contact structures SC2 may be elongated in the second direction D2 and at least partially disposed on the first active region A1, and each of the third slot contact structures SC3 may be elongated in the second direction D2 and at least partially disposed on the second active region A2.
  • the two second slot contact structures SC2 may be disposed between the third gate structure GS3 and the first gate structure GS1 in the first direction D1 and be disposed between the third gate structure GS3 and the second gate structure GS2 in the first direction D1 respectively.
  • the two third slot contact structures SC3 may be disposed between the third gate structure GS3 and the first gate structure GS1 in the first direction D1 and be disposed between the third gate structure GS3 and the second gate structure GS2 in the first direction D1 respectively.
  • a length of the second slot contact structure SC2 in the second direction D2 and a length of the third slot contact structure SC3 in the second direction D2 may be respectively less than a length of the first slot contact structure SC1 in the second direction D2.
  • the dielectric layer 40 mentioned above may be further disposed on the third gate contact structures GC3, the second slot contact structures SC2, and the third slot contact structures SC3.
  • Two openings V4 may penetrate the dielectric layer 40 on the second slot contact structures SC2 respectively, and two openings V5 may penetrate the dielectric layer 40 on the third slot contact structures SC3 respectively.
  • the conductive line L3 may be electrically connected with the second slot contact structures SC2 via the openings V4, and the conductive line L4 may be electrically connected with the third slot contact structures SC3 via the openings V5.
  • the conductive line L1, the conductive line L2, the conductive line L3, and the conductive line L4 mentioned above may be elongated in the first direction D1 respectively and disposed parallel to one another.
  • the dummy conductive lines DL may be disposed between the conductive line L1, the conductive line L2, the conductive line L3, and the conductive line L4 according to some considerations, and the dummy conductive lines DL may be electrically floating or be connected to a voltage source according to the design considerations.
  • the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, and the dummy conductive lines DL may be formed concurrently by the same manufacturing process and have the same composition (may be a part of a patterned conductive layer M1 respectively, for example), but not limited thereto.
  • a multiple patterning process such as a self-aligned double patterning (SADP) process may be used to form the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, and the dummy conductive lines DL with smaller spacing therebetween because the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, and the dummy conductive lines DL may be elongated in the same direction, and the occupied area of the semiconductor device 101 may be reduced by this approach.
  • SADP self-aligned double patterning
  • the layout design of the semiconductor device 101 shown in FIG. 1 may be regarded as a standard cell, and one or more transistor structures may be included in this standard cell for providing required operation performance.
  • the first gate structure GS1 disposed on the first active region A1 and the second gate structure GS2 disposed on the first active region A1 may be a gate electrode G1 of a first transistor T1
  • the first gate structure GS1 disposed on the second active region A2 and the second gate structure GS2 disposed on the second active region A2 may be a gate electrode G2 of a second transistor T2
  • the gate electrode G1 of the first transistor T1 may be electrically connected with the gate electrode G2 of the second transistor T2 by the first gate structure GS1 disposed on the isolation structure IS and the second gate structure GS2 disposed on the isolation structure IS.
  • first slot contact structure SC may be electrically connected with a first source/drain region SD11 (such as the epitaxial region 32 described above) of the first transistor T1 and a first source/drain region SD21 (such as an epitaxial region formed in the second active region A2, not shown) of the second transistor T2.
  • the second slot contact structure SC2 may be electrically connected with a second source/drain region SD12 (such as another epitaxial region 32 formed in the first active region A1) of the first transistor T1.
  • the third slot contact structure SC3 may be electrically connected with a second source/drain region SD12 (such as another epitaxial region formed in the second active region A2, not shown) of the second transistor T2.
  • the semiconductor device 101 may be regarded as an inverter, such as a first inverter INV1
  • the first transistor T1 may be a P-type transistor in the first inverter INV1
  • the second transistor T2 may be an N-type transistor in the first inverter INV1, but not limited thereto.
  • the length of the first gate contact structure GC1 in the second direction D2 may be substantially equal to a length of the first gate contact structure GC1 in the first direction D1
  • the length of the second gate contact structure GC2 in the second direction D2 may be substantially equal to a length of the second gate contact structure GC2 in the first direction D1.
  • the shape of the first gate contact structure GC1 and the shape of the second gate contact structure GC2 in a top view diagram of the semiconductor device 101 may be square, round, or other suitable shapes.
  • the length of the first gate contact structure GC1 in the second direction D2 and the length of the second gate contact structure GC2 in the second direction D2 may be less than a pitch between the conductive line L1 and the dummy conductive line DL in the second direction D2.
  • the pitch described above may be equal to the sum of the spacing between the conductive line L1 and the dummy conductive line DL adjacent to the conductive line L1 and the width of the conductive line L1 in the second direction D2, but not limited thereto.
  • the dummy conductive line DL disposed adjacent to the conductive line L1 does not overlap the first gate contact structure GC1 and the second gate contact structure GC2 in the third direction D3.
  • FIG. 6 is a schematic drawing illustrating a semiconductor device according to another embodiment of the present invention.
  • the difference between the semiconductor device in this embodiment and the semiconductor device in the first embodiment described above is that the first gate structure GS1 and the second gate structure GS2 in this embodiment may respectively include an interfacial layer 21, a gate dielectric layer 22, a barrier layer 23, a work function layer 24, a gate material layer 25, and a gate capping layer 26.
  • the interfacial layer 21 may include silicon oxide or other suitable dielectric materials.
  • the gate dielectric layer 22 may include a high dielectric constant (high-k) dielectric layer, such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), or other suitable high-k materials.
  • high-k dielectric layer such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), or other suitable high-k materials.
  • the barrier layer 23 and the work function layer 24 may respectively include tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), or other suitable N-type work function materials and/or P-type work function materials.
  • the gate material layer 25 may include a low resistivity metallic material, such as aluminum, tungsten, copper, titanium aluminide, or other suitable metallic conductive materials having relatively lower resistivity.
  • the gate capping layer 26 may include silicon nitride, silicon carbonitride, or other suitable insulation materials. It is worth noting that the above-mentioned compositions of the first gate structure GS1 and the second structure GS2 in this embodiment may also be applied to other embodiments of the present invention according to some considerations.
  • FIG. 7 is a schematic drawing illustrating a semiconductor device 102 according to a second embodiment of the present invention.
  • the difference between the semiconductor device 102 in this embodiment and the semiconductor device in the first embodiment described above is that the first gate contact structure GC1 and the second gate contact structure GC2 in this embodiment may be arranged misaligned with each other in the first direction D1.
  • the first gate contact structure GC1 may not be flush with the second gate contact structure GC2 in the first direction D1 for reducing negative influence generated by the extremely short distance between the first gate contact structure GC1 and the first slot contact structure SC1 and the extremely short distance between the second gate contact structure GC2 and the first slot contact structure SC1 in this embodiment.
  • the semiconductor device 102 in this embodiment may further include a second conductive line (such as a conductive line L5) disposed on the dielectric layer 40 and elongated in the first direction D1.
  • a second conductive line such as a conductive line L5
  • a part of the conductive line L5 may be disposed on the second gate contact structure GC2, and the conductive line L5 may be electrically connected with the second gate contact structure GC2 via the opening V2.
  • the first gate contact structure GC1 and the second gate contact structure GC2 in this embodiment may be arranged misaligned with each other in the first direction D1, and the first gate contact structure GC1 and the second gate contact structure GC2 may be electrically connected with different conductive lines respectively.
  • the length of the first gate contact structure GC1 in the second direction D2 and the length of the second gate contact structure GC2 in the second direction D2 may be less than a pitch between the conductive line L1 and the conductive line L5 in the second direction D2.
  • the pitch described above may be equal to the sum of the spacing between the conductive line L1 and the conductive line L5 and the width of the conductive line L1 in the second direction D2, or the pitch described above may be equal to the sum of the spacing between the conductive line L1 and the conductive line L5 and the width of the conductive line L5 in the second direction D2, but not limited thereto.
  • the semiconductor device 102 may be regarded as an inverter, such as a second inverter INV2, but not limited thereto.
  • FIG. 8 is a top view schematic drawing illustrating a semiconductor device 103 according to a third embodiment of the present invention
  • FIG. 9 is a cross-sectional diagram taken along a line D-D' in FIG. 8
  • FIG. 10 is a cross-sectional diagram taken along a line E-E' in FIG. 8
  • FIG. 11 is a cross-sectional diagram taken along a line F-F' in FIG. 8
  • FIG. 12 is a cross-sectional diagram taken along a line G-G' in FIG. 8 .
  • the semiconductor device 103 may further include a fourth gate structure GS4, a fourth gate contact structure GC4, a conductive line L6, a conductive line L7, a conductive line L8, an opening V6, and an opening V7.
  • the fourth gate structure GS4 may be elongated in the second direction D2 and disposed on the first active region A1, the second active region A2, and the isolation structure IS.
  • the fourth gate structure GS4 may be located between the first gate structure GS1 and the third gate structure GS3 in the first direction D1.
  • the first gate structure GS1, the second gate structure GS2, the third gate structure GS3, and the fourth gate structure GS4 may be formed concurrently by the same manufacturing process and have the same composition, the same width, and equal spacing, but not limited thereto.
  • the fourth gate contact structure GC4 may be partially disposed on and electrically connected with the fourth gate structure GS4.
  • the fourth gate contact structure GC4, the first gate contact structure GC1, and the second gate contact structure GC2 may be formed concurrently by the same manufacturing process, and the compositions of the first gate contact structure GC1, the second gate contact structure GC2, and the fourth gate contact structure GC4 may be identical to one another, but not limited thereto.
  • the semiconductor device 103 in this embodiment may include three second slot contact structures SC2 disposed between the first gate structure GS1 and the fourth gate structure GS4, between the fourth gate structure GS4 and the third gate structure GS3, and between the second gate structure GS2 and the third gate structure GS3 respectively, and the semiconductor device 103 may include three third slot contact structures SC3 disposed between the first gate structure GS1 and the fourth gate structure GS4, between the fourth gate structure GS4 and the third gate structure GS3, and between the second gate structure GS2 and the third gate structure GS3 respectively, but not limited thereto.
  • the dielectric layer 40 in this embodiment may be disposed on the first gate contact structure GC1, the second gate contact structure GC2, the third gate contact structures GC3, the fourth gate contact structure GC4, the first slot contact structure SC1, the second slot contact structures SC2, and the third slot contact structures SC3.
  • the opening V6 may penetrate the dielectric layer 40 on the fourth gate contact structure GC4 and expose a part of the fourth gate contact structure GC4, and the opening V7 may penetrate the dielectric layer 40 on the first slot contact structure SC1 and expose a part of the first slot contact structure SC1.
  • the conductive line L6, the conductive line L7, and the conductive line L8 may be disposed on the dielectric layer 40 and elongated in the first direction D1 respectively.
  • a portion of the conductive line L6 may be disposed on the fourth gate contact structure GC4, and the conductive line L6 may be electrically connected with the fourth gate contact structure GC4 via the opening V6. Additionally, another portion of the conductive line L6 may be disposed on the second gate contact structure GC2, and the conductive line L6 may be electrically connected with the second gate contact structure GC2 via the opening V2. In other words, the second gate structure GS2 and the fourth gate structure GS4 may be electrically connected with each other by the second gate contact structure GC2, the conductive line L6, and the fourth gate contact structure GC4.
  • the conductive line L7 may be electrically connected with the first slot contact structure SC1 and the second slot contact structure SC2 via the opening V3 and the opening V4 respectively, and the first slot contact structure SC1 may be electrically connected with one of the second slot contact structures SC2 by the conductive line L7 accordingly.
  • the conductive line L8 may be partially disposed on the first slot contact structure SC1 located on the second active region A2, and the conductive line L8 may be electrically connected with the first slot contact structure SC1 via the opening V7.
  • the conductive line L1, the conductive line L6, the conductive line L7, the conductive line L8, and the dummy conductive lines DL may be formed concurrently by the same manufacturing process, and the compositions of the conductive line L1, the conductive line L6, the conductive line L7, the conductive line L8, and the dummy conductive lines DL may be identical to one another (may be a part of the patterned conductive layer M1 respectively, for example), but not limited thereto.
  • the semiconductor device 103 in this embodiment may be an inverter, and the layout design of standard cell corresponding to the semiconductor device 103 may be simplified and/or the area occupied by the standard cell may be reduced by disposing the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, and the dummy conductive lines DL elongated in the same direction and disposing the first gate contact structure GC1 and the second gate contact structure GC2 at the two opposite sides of the first slot contact structure SC1.
  • FIG. 13 is a schematic drawing illustrating a semiconductor device 104 according to a fourth embodiment of the present invention.
  • the semiconductor device 104 in this embodiment may include a plurality of the first inverters INV1 connected with one another for composing a ring oscillator.
  • first inverters INV1 may be arranged in the first direction D1, one of the third gate structures GS3 may be shared by the first inverters INV1 adjacent to each other, and the first active region A1, the second active region A2, the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, and the dummy conductive lines DL may be shared by the first inverters INV1 repeatedly disposed in the first direction D1 for forming the ring oscillator.
  • the first inverter INV1 may be regarded as a part of the ring oscillator shown in FIG. 13 , but the present invention is not limited to this.
  • the first inverter INV1 may also be used to form a semiconductor structure with other functions.
  • FIG. 14 is a schematic drawing illustrating a semiconductor device 105 according to a fifth embodiment of the present invention.
  • the semiconductor device 105 in this embodiment may include a plurality of the second inverters INV2 connected with one another for composing a ring oscillator.
  • Two or more second inverters INV2 may be arranged in the first direction D1, one of the third gate structures GS3 may be shared by the second inverters INV2 adjacent to each other, and the first active region A1, the second active region A2, the conductive line L1, the conductive line L2, the conductive line L3, the conductive line L4, the conductive line L5, and the dummy conductive lines DL may be shared by the second inverters INV2 repeatedly disposed in the first direction D1 for forming the ring oscillator.
  • the gate contact structures may be disposed adjacent to the slot contact structure connected with different source/drain regions for simplifying the layout design of the standard cell corresponding to the semiconductor device and/or reducing the area occupied by the standard cell.
  • the conductive lines corresponding to the gate contact structures and the slot contact structures in the standard cell may be accordingly elongated in the same direction for simplifying the layout design, and the area occupied by the standard cell may be further reduced because a multiple patterning process may be used to form the conductive lines with smaller spacing therebetween.

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US11552001B2 (en) 2023-01-10
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US20230112835A1 (en) 2023-04-13
US12087666B2 (en) 2024-09-10

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