Classifications

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  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
  • H01L33/58—Optical field-shaping elements
  • H01L33/60—Reflective elements
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  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0232—Optical elements or arrangements associated with the device
  • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
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  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
  • H01L33/483—Containers
  • H01L33/486—Containers adapted for surface mounting
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/02208—Mountings; Housings characterised by the shape of the housings
  • H01S5/02216—Butterfly-type, i.e. with electrode pins extending horizontally from the housings
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/0225—Out-coupling of light
  • H01S5/02255—Out-coupling of light using beam deflecting elements
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/0225—Out-coupling of light
  • H01S5/02257—Out-coupling of light using windows, e.g. specially adapted for back-reflecting light to a detector inside the housing
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
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  • H01S5/0233—Mounting configuration of laser chips
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  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/0235—Method for mounting laser chips
  • H01S5/02355—Fixing laser chips on mounts
  • H01S5/0237—Fixing laser chips on mounts by soldering
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  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
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  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/481—Disposition
  • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
• • H—ELECTRICITY
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  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73265—Layer and wire connectors
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  • H01L2224/93—Batch processes
  • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
• • H—ELECTRICITY
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  • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/161—Cap
  • H01L2924/1615—Shape
  • H01L2924/16195—Flat cap [not enclosing an internal cavity]
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  • H01L2933/0008—Processes
  • H01L2933/0033—Processes relating to semiconductor body packages
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  • H01L2933/0008—Processes
  • H01L2933/0033—Processes relating to semiconductor body packages
  • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
  • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
  • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

• the invention relates to a component arrangement, a package and a package arrangement and method for manufacturing.
• components or components for example, optical components that emit or absorb light to arrange in a housing.
• the component assembly can be used to make a package.
• a method for producing such a component arrangement is known, for example, from the document WO 2011/035783 A1.
• a spacer is arranged such that the spacer surrounds a space in which a component is arranged.
• the installation space is closed by placing a cover substrate on the spacer. With the cover substrate, a translucent outlet opening may be provided through which light can be emitted or received.
• the installation space facing wall surfaces of the spacer can be provided with a metalization tion to provide a light-reflecting coating.
• Document WO 2016/055520 A1 describes the manufacture of a package for a laser component with a housing comprising a carrier having a cavity with a bottom surface and a side wall.
• the cavity expands starting from the bottom surface.
• a laser chip on the bottom surface is arranged, the emission direction is oriented parallel to the bottom surface.
• a reflective element is also arranged, which abuts an edge between the Bodenfiambae and the side wall.
• a reflective surface of the reflective element makes an angle of 45 degrees with the bottom surface of the cavity.
• the emission direction also includes an angle of 45 degrees with the reflective surface of the reflective element.
• the object of the invention is to specify a component arrangement, a package and a package arrangement and method for producing, with which an improved light conduction or deflection of light beams is provided in a construction space with an optical component,
• a package and a package assembly according to independent claims 1, 11 and 13 are provided. Furthermore, methods for building a component arrangement, a package as well as a package arrangement according to the independent claims 10, 14 and 15 are provided.
• a component arrangement which has the following: a carrier substrate, a spacer which is arranged on the carrier substrate in a surrounding space and has an outlet opening on a side remote from the carrier substrate; an optical component which is arranged in the installation space; a contact connection, which connects the optical component with external contacts electrically conductive, which are arranged outside the installation space; a cover substrate, which is arranged on the spacer and with which the outlet opening is translucently covered sig; and a light-reflecting surface formed on an anisotropically etched silicon member and disposed in the construction space as an inclined surface at an angle of about 45 degrees to the installation space facing surface of the support substrate, such that light irradiated horizontally onto the light-reflecting surface becomes vertical Direction through the opening and the cover substrate can be emitted and vice versa.
• a package is provided with a component arrangement and a housing in which the component arrangement is accommodated, as well as a package arrangement which has a planar arrangement of a plurality of packages.
• a further aspect relates to a method for producing a component arrangement with the following steps: producing an anisotropically etched silicon component from a silicon monocrystal by means of anisotropic etching, wherein the silicon monocrystal in this case is inclined by about 9.7 degrees to the 100-crystal orientation, in such a way in that a 1 1 1 crystal plane is formed with a slope of about 45 degrees; and fabricating a device assembly using the anisotropically etched Sifiziumbauteils, wherein with the 1 11 -Cristallebene with the Beveled by about 45 degrees in the component assembly a lichtrefiektierende surface is formed.
• a method of manufacturing a package and a method of manufacturing a package assembly, wherein the package / package assembly is fabricated using, for example, wafer level packaging.
• the installation space provided in the component arrangement to redirect light beams extending in the horizontal direction at the approximately 45 degrees inclined light-reflecting surface in the horizontal direction, and vice versa.
• emitted light can be deflected from the horizontal direction in the vertical direction so as to deliver the light rays through the exit opening through.
• incident light in the vertical direction through the exit opening can be deflected at the light-reflecting surface in the horizontal direction.
• the light-reflecting surface is provided with the anisotropically etched silicon component as the surface of this component.
• the optical component can be designed as a light-emitting or light-absorbing component, for example as a light-emitting diode or light-absorbing photodiode, for example an avalanche photodiode or laser diode.
• the light-emitting component can be designed to emit light beams in directed and bundled form, for example in the form of substantially directed laser radiation with centric emission of the intensity maximum with optionally existing radiation divergence (beam expansion).
• the proposed technology makes it possible to arrange the optical component in the installation space such that the exit of the emitted light beams or the entry of the light beams to be received in the vertical direction can take place.
• the optical component in order to dispense light beams in the vertical direction (relative to the surface of the carrier substrate), it is not necessary to arrange the optical component upright in the installation space, as is provided in the prior art (compare, for example) US Pat. No. 7,177,331 B2).
• the contact connection may have a through-connection through the carrier substrate, wherein the external contacts may be arranged on the underside of the carrier substrate.
• a contact connection guided laterally out of the installation space can be provided, for example, on the surface of the carrier substrate facing the installation space, in particular in such a way that the laterally led out contact connection is formed between the carrier substrate and the spacer.
• the contact connection may comprise a plurality of individual contact connections.
• a contact surface of the anisotropically etched silicon component can run substantially parallel to the surface of the carrier substrate facing the installation space.
• the light-reflecting surface is inclined at an angle of about 45 degrees to the support surface.
• the anisotropically etched silicon component may be arranged in the space enclosed by the spacer.
• the anisotropically etched silicon component on which the anderreflek animal surface is provided be arranged in the space separated and spaced from the spacer, in particular such that there is no physical contact between the anisotropically etched silicon component and the spacer which surrounds the space.
• the spacer may be at least partially formed.
• the anisotropically etched component forms the spacer partially or completely. It may be provided in one embodiment that the spacer surrounding the installation space completely surrounds the installation space and is formed completely from the anisotropically etched silicon component, for example as a one-piece anisotropically etched silicon component.
• an inner wall surface of the spacer facing the installation space has an inclination of approximately 45 degrees at least in the region of the light-reflecting surface.
• the Abstandshaiter may be formed as a one-piece frame surrounding the space circumferentially.
• a first wall surface of the spacer which faces the installation space and is disposed outside a region with the light-reflecting surface, may be inclined to the vertical direction at a first angle other than 45 degrees. While the the The space facing wall surface of the spacer in the region of the light-reflecting surface has an inclination of about 45 degrees, the first wall surface is outside the range with the light-reflecting surface at a different angle therefrom, which is for example about 64.5 degrees.
• the first wall surface of the spacer may be arranged opposite the light-reflecting surface.
• a second, different from the first wall surface of the spacer, which faces the construction space and is arranged outside the area with the light-reflecting surface may be inclined to the vertical direction with a second different from 45 degrees angle, which is different from the first angle.
• the first / or the second wall surface, which have a different angle of inclination from 45 degrees, can be arranged in a section of the spacer formed by the anisotropically etched silicon component or outside such a section.
• the second angle may be, for example, about 55.3 degrees.
• the second wall surface may be disposed in a portion of the spacer adjacent to the light-reflecting surface and / or the first wall surface.
• Opposing wall surfaces may be formed with the second Ne Trentswin angle.
• the wall surfaces other than 45 degrees may be made at different angles.
• the spacer may be formed by means of the anisotropically etched silicon component as a one-piece or multi-piece frame, which completely surrounds the space completely.
• the frame may have a substantially trapezoidal shape, be it in the region of an upper and / or a lower opening of the opening, which is surrounded by the frame. If the upper and lower openings each have a substantially trapezoidal shape, edges of the upper and lower openings can run in pairs in parallel, be it on one or more sides of the opening, in particular also on all sides.
• the trapezoidal shape may not be formed over the entire width of the aperture in one embodiment, but substantially over a width of less than 1/3 of the total width of the aperture.
• the opening angles (in corner areas of the aperture) on the 45 degree mirror plane side may each be about 83.2 degrees. At the opposite side, the angles are each about 96.8 degrees. It may be provided a design in which a plurality of openings of this type are provided in the anisotropically etched silicon component, which are each formed a separately formed space for receiving one or more optical components,
• the cover substrate can at least partially fill the installation space.
• the cover substrate can fill the space partially or completely.
• epoxy resin or silicone can be introduced into the installation space as a cover substrate.
• the space is free from the cover substrate, wherein the space can then be designed as a cavity in which the optical component is arranged. In particular, a section of the cavity below the outlet opening may be free of the cover substrate.
• the light-reflecting surface may have a surface-side mirroring.
• the surface-side mirroring can be produced for example by means of a metallization or a dielectric mirror.
• the optical component may have a lateral optical output / input through which light can emerge / enter in the horizontal direction.
• the deflection of the emerging or emerging light rays takes place on the light-reflecting surface, such that a deflection takes place between the horizontal and vertical direction or vice versa.
• the optical component is designed as a light-emitting diode, the emitted light rays exit through a lateral optical output.
• the incident light beams enter in the horizontal direction through a lateral optical input, for example an entrance window.
• the optical component can be arranged on a submount which is arranged on the carrier substrate.
• the submount can be formed, for example, from silicon carbide or aluminum nitride.
• the anisotropically etched silicon component by means of wet-chemical etching, for example by means of etching with potassium hydroxide (KOH).
• KOH potassium hydroxide
• Another suitable etching solution for the anisotropic etching of silicon is, for example, tetramethylammonium hydroxide (TMAH).
• one or more circumferential silicon frames, entire cap substrates, and / or a single or multiple elements may be fabricated with a 45 degree inclined reflection surface at the wafer level. the.
• the advantage is that many components / caps can be produced simultaneously at the wafer level.
• the individual caps for the house arise after separation, for example by sawing the cap substrate.
• the packaging of the device can be done by applying an isolated cap to a board on which a chip or device is preassembled.
• the components may also be preassembled in a utility, that is, several components are already mounted on a carrier substrate, which are then housed by the application of individual caps or cap arrays (isolated use with multiple cap structures from a cap substrate produced in the wafer level).
• Wafer-level packaging refers to packaging all components on a wafer in one step with a wafer-form overlay substrate. For example, this may be the case if components are completely preassembled on a substrate contacted by a substrate, for example a silicon substrate in wafer form, and then all components are simultaneously housed by bonding a cap wafer. Individual packages are then created by subsequent separation of the composite.
• the cover substrate can be made, for example, of borosilicate glass such as Bofofloat33 or Mepax from Schott AG, quartz glass, sapphire glass or else other glasses such as AF32, D263T, BK7 or B270 from Schott AG; Eagle XG or Pyrex from Corning; SD2 from Hoya or AS-A1 from Asahi.
• the cover substrate may also be formed of silicon or germanium, for example in applications in the IR range.
• the cover substrate may additionally have a substrate coating, for example an antireflection coating.
• the coatings can be designed for different wavelength ranges and be designed on one side or on both sides. It is also possible to provide filter coatings and / or opaque structures which are opaque to different wavelength ranges.
• the integration of optical elements may be provided, for example, lenses on the top substrate.
• lenses on the top substrate for example, kon vexe lenses made of polymer, vitreous materials, silicon or germanium come into consideration here.
• the use of microstructured Fresnel lenses is also possible.
• One or more plated-through holes for the electrical contact of the optical component are provided in the carrier substrate.
• the rear-side contacts allow subsequent mounting in the SMD design, for example by tin / silver wave soldering or fitting with electrically conductive adhesives.
• the carrier substrate may consist, for example, of silicon, ceramics such as, for example, aluminum nitride, silicon carbide, aluminum oxide, LTTC (Low Temperature Cofired Ceramics) or HTCC (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates.
• ceramics such as, for example, aluminum nitride, silicon carbide, aluminum oxide, LTTC (Low Temperature Cofired Ceramics) or HTCC (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates.
• metal substrates for example, IMS (insulated metal substrates) made of copper, aluminum or other metals can be provided.
• carrier substrates made of plastics such as FR4 is also conceivable.
• a connection between spacer and carrier substrate can be effected, for example, via a solder bond, preferably via a eutectic bond.
• a metal combination in preferably eutectic composition is applied to the carrier substrate or the back of the spacer, for example gold and tin, copper and tin, gold and germanium, tin and silver, gold and indium, copper and silver or gold and silicon, which in a soldering process forms a eutectic connection phase and spacer connects with carrier substrate.
• Spacer and carrier substrate are provided for the soldering process with a corresponding base metallization.
• the metal combination for the eutectic cal joining can be provided for example as a pre-form. Alternatively, the metal combination can be applied as a paste or galvanically on one of the joining partners.
• a direct bonding process can also be used.
• This may be a direct fusion bond which is hydrophobic or hydrophilic based on the surface character of the bonding partners.
• the two bond partners are first connected to each other via a pre-bond through van der Waals bonds. Through a subsequent annealing step, covalent bonds are then formed in the bond interface.
• the fusion bond can also be plasma activated. leads his. This makes it possible to significantly reduce the temperature load during annealing.
• an anodic bonding may be provided.
• a reactive bonding process can also be used.
• a metal stack of alternating layers is applied.
• This metal stack may be provided by, for example, deposition methods such as sputtering or in the form of films.
• An electrical or a laser-induced pulse leads in the short term to the generation of a highly thermal reaction, which "welds" the two bond partners together.
• the metal layers are bilayer periods, for example of palladium and aluminum or of copper oxide and aluminum.
• solid-liquid interdiffusion bonding is possible, for example, metal combinations of gold and indium, gold and tin or copper and tin.
• the bonding process during a Temper Marins is determined by the diffusion of the one Bondpartners in the other. The actual connection phase then resists higher temperatures later.
• permanent connections can be made by joining, for example, gold with gold, copper with copper or aluminum with aluminum by means of (for example) thermal compression bonding. Glass frit bonding may also be provided.
• a laser welding method for connecting carrier substrate and spacers can be used. Also conceivable is the use of epoxy resins, silicones or other adhesives.
• a direct bonding method can be used for the connection of spacer and cover substrate.
• Such methods are, for example, the anodic bond or a fusion bond.
• reactive bonding or an adhesive bond can be used.
• soiid-liquid interdiffusion bonding comes into question.
• Laser welding is also suitable for joining spacer and cover substrate. Here, two substrates are brought into “optical contact” and then welded with a laser. It is also conceivable to use all the abovementioned joining methods for spacer and carrier substrate for the joining of spacer and cover substrate as well.
• the embodiments described in connection with the component arrangement may be provided correspondingly in connection with the method for producing the component arrangement.
• FIG. 1 shows a component arrangement in which an optical component is arranged in a construction space and connected via a contact connection through a carrier substrate with external contacts;
• FIG. 2 shows a component arrangement in which an optical component is arranged in a construction space and is connected to outside contacts via a laterally leading out contact connection;
• FIG. 3 is a schematic representation of a component arrangement in which the installation space with the optical component is filled with a cover substrate;
• Fig. 4 is a schematic representation of a component arrangement, in which with the construction space with the optical component filling deck substrate, a jacket is formed;
• Figure 5 is a schematic representation of a component arrangement in which in the space a light-reflecting surface is provided by means of an anisotropically etched silicon component BE, which is spaced from a spacer disposed in the space.
• Fig. 6 is a schematic representation of a frame spacer formed from an anisotropically etched silicon device
• FIG. 7a a light microscope view of an etched frame structure in which a masking opening is selected for an anisotropic wet-chemical etching process with a compensation structure;
• 7b is a light microscope view of another etched frame structure, in which a masking opening is selected for an anisotropic wet-chemical etching process with egg ner compensation structure.
• FIG. 8 shows a schematic illustration of a section of a wafer having a plurality of openings, each of which can be used to form a component arrangement in order to produce a capping array
• FIG. 9 shows a schematic illustration of spacers, which are each formed with an anisotropically etched silicon component, wherein a central positioning of chips gel Formation in a frame geometry allows a centric exit / entry of the light;
• FIG. 10 shows a schematic representation of an arrangement with a spacer formed by an anisotropically etched silicon component, on which a cover substrate is arranged, wherein the spacer has on a lower side a back structuring surface, for example a metallization;
• FIG. 11 is a schematic representation of an arrangement in which the light-reflecting surface opposite a portion of a glass fiber for Lichteinkopplung / -auskopplung is arranged.
• Figure 12 is a schematic representation of an arrangement in which two individual mirror elements are arranged in a housing.
• FIG. 13 shows a schematic illustration of two components which have been manufactured in use or by means of wafer level packaging
• Figure 14 is a schematic representation of an arrangement in which the space is formed by a spacer element, which has a Flankenwinkei the mirror surfaces of about 54.7Grad;
• FIG. 15 shows a schematic representation of a component in which the spacer element and the carrier substrate are manufactured in one piece and the through contacts are provided by means of a dry etching method
• FIG. 16 shows a schematic representation of a component in which the spacer element and the carrier substrate are manufactured in one piece and the through contacts are provided by means of a wet-chemical etching method
• FIG. 17 shows a schematic representation of a component in which the walls of the construction space are formed approximately perpendicularly with the exception of a 45-degree mirror plane;
• FIG. 18 shows a schematic illustration of a component arrangement in which a lens is arranged on the cover substrate
• FIG. 19 shows a schematic representation of a component arrangement with a peripheral spacer element with mirror plane in combination with a single mirror element
• FIG. 20 is a schematic representation of a component arrangement in which a lower opening in the spacer, which is embodied as an anisotropically etched silicon component, is designed with a nearly vertical chamfer; and
• 21 is a schematic representation of a component arrangement in which a lower opening in the spacer, which is designed as an anisotropically etched silicon component, is designed with an undercut relative to the surface of the spacer.
• 1 shows a component arrangement in which an optical component 2 is arranged in a construction space 1 a on a carrier substrate 1.
• the optical component 2 is, for example, a light-emitting or light-receiving diode, for example a laser diode or a photodiode.
• the optical component 2 is mounted in the exemplary embodiment on a submount 5, for example a submount of silicon carbide or aluminum nitride.
• the optical component 2 can be arranged directly on the carrier substrate 1.
• the assembly of the optical component 2 on the submount 5 or directly on the carrier substrate 1 by means of eutectic soldering done, for example, gold and tin.
• eutectic soldering done, for example, gold and tin.
• other methods such as gold or indium bonding or Sinterbondvon can be used.
• the chip can be mounted either via a flip-chip process, via bonding with wire bonds or a ground contact in combination with wire bonds.
• the silicon spacer 3 is made by anisotropic KOH etching from a silicon single crystal inclined by about 9.7 degrees to the crystal orientation (off-oriented). As a result, an 11 1 crystal plane is formed which has a slope 6 at an angle of about 45 degrees to the surface. The opposite plane then forms at an angle of about 64.5 degrees.
• the lateral crystal planes may have an angle of about 55.3 degrees.
• the spacer 3 which is embodied as an anisotropically etched silicon component, has a metallic mirror coating 6a in the embodiment shown.
• another optical (light-reflecting) layer may be provided, for example a dielectric mirror for certain wavelengths.
• aluminum may be used in the UV range, gold in the visible range, and gold in the IR / NIR range.
• a metallic mirror coating of copper is advantageous from the "red" wavelength range (wavelengths greater than about 600 nm).
• the oblique side walls in a cavity may also be provided with different coatings.
• the side walls which are different from 45 degrees, for the desired wavelength range can be provided with a particularly opaque / light-absorbing layer in order to avoid reflections in the construction space.
• the 45 degree inclined naturally grown monocrystalline 11 1 planes (light reflecting surfaces / mirror surfaces) thus produced by the wet-chemical etching process described above are very smooth compared to other manufacturing processes such as machining or dry etching processes. This results in a very low-dispersion and low-loss deflection of the beam.
• the optical component 2 mounted on the carrier substrate 1 may be a side-emitting component, for example a laser diode.
• the slope 6 of 45 degrees allows that from the optical component 2 laterally horizontally exiting light can be emitted vertically by corre sponding deflection.
• the cover substrate 4 can be made, for example, of borosilicate glass such as Borofloat33 or Mempax from Schott AG, quartz glass, sapphire glass or else other glasses such as AF32, D263T, BK7 or B270 from Schott AG; Eagle XG or Pyrex from Corning; SD2 from Hoya; Consist of Asahi EN-A1.
• the cover substrate 4 may also consist of silicon or germanium, for example, in applications in the IR range.
• the cover substrate 4 may additionally have a substrate coating, for example an antireflection or a filter coating.
• the coatings can be designed for different wavelength ranges, one-sided or two-sided and possibly structured. It is also possible to use opaque structured coatings for the formation of, for example, apertures for the wavelength ranges.
• the integration of optical elements may be provided, for example, lenses on the cover substrate 4.
• lenses for example, convex lenses made of polymer, glasses or other glassy materials, silicon or germanium in question (see Fig. 18).
• microstructured Fresnel lenses is also possible.
• the carrier substrate 1 can be made, for example, of silicon, ceramics such as, for example, aluminum nitride, silicon carbide, aluminum oxide, LTTC ceramics (Low Temperature Cofired Ceramics) or HTCC ceramics (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates consist.
• ceramics such as, for example, aluminum nitride, silicon carbide, aluminum oxide, LTTC ceramics (Low Temperature Cofired Ceramics) or HTCC ceramics (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates consist.
• metal substrates for example, IMS (insulated metal substrates) of copper, aluminum or other metals may be provided.
• the use of carrier substrates made of plastics such as FR4 is conceivable.
• a connection 9 of spacer 3 and carrier substrate 1 can take place, for example, via a solder bond, preferably via a eutectic bond.
• a metal combination in a corresponding eutectic composition such as gold and tin, copper and tin, gold and germanium, tin and silver, gold and indium, copper and silver, tin with silver and copper or even gold and silicon applied. In the later soldering process, this forms a eutectic connection phase between spacer 3 and carrier substrate 1.
• a layer of pure titanium, tungsten titanium or tungsten titanium nitride below the applied metal stack.
• the bonding partner must be provided with a counter-metallization for the joining process in order to ensure good wetting of the connecting phase forming in the soldering process.
• solders for the joining of carrier substrate 1 and spacers 3 can also be used.
• a sintering process may be provided, for example silver or gold sintering.
• alloy stop under the actual connection phase.
• layers of platinum, nickel or even alloys of chromium and nickel are suitable for this purpose.
• a direct bonding process can also be used.
• This may be a direct fusion bond which is hydrophobic or hydrophilic based on the surface character of the bonding partners.
• the two bond partners are first connected to each other via a pre-bond through van der Waals bonds. By a subsequent annealing step then form in the Bond interface covalent bonds.
• the fusion bond can also be plasma-activated. This makes it possible to significantly reduce the temperature load during annealing.
• an anodic bonding can also be provided. The latter method offers the advantage that the demands on the surface quality of the bond partners are less demanding compared to fusion bonding.
• a reactive bonding process can also be used.
• a metal stack of alternating metallic layers is applied.
• An electrical or a laser-induced pulse leads in the short term to the generation of a high-thermal reaction, which "welds" the two bond partners together.
• the metal layers are bilayer periods, for example of palladium and aluminum or of copper oxide and aluminum.
• solid-liquid interdiffusion bonding for example with metal combinations of gold and indium, gold and tin or also copper and tin is considered.
• the bonding process during a tempering step is determined by the diffusion of one Bondpartners in the other. The actual connection phase then resists higher temperatures later.
• glass frit bonding may also be provided.
• a di rect bonding method can be used for the connection 10 of spacer 3 and cover substrate 4.
• Such methods are, for example, the anodic bond or a fusion bond.
• the direct joining of silicon with the cover substrate may be provided from an alkaline glass.
• the anodic joining of aluminum with the cover substrate of an alkaline glass is possible.
• the reflective coating on the 45-degree mirror surface is not structured, that is to say that the upper side of the silicon spacer is completely coated with aluminum.
• reactive bonding or an adhesive bond can be used.
• solid-liquid interdiffusion bonding is also an option here.
• Laser welding is also suitable for joining spacers and cover substrate. Ffierbei brings two substrates into “optical contact” and then welds them with a laser. The joining of spacer and cover substrate can also be realized as a thermocompression bond, for example of Metallko binatioinen gold with gold, copper with copper or aluminum with aluminum.
• FIG. 2 shows the arrangement of the optical component 2 with a laterally made contact.
• printed conductors 11 are applied to the carrier substrate 1, which are guided below the spacer 3 to the outside.
• the spacer 3 and the performed contact are separated by an electrical insulation layer 12 from each other.
• This layer may consist, for example, of SiOx or silicon nitride.
• the connection of the cap and the board or the insulating layer is produced, for example, by a eutectic metal bond.
• the construction space 1a is decayed by, for example, an epoxy resin or silicone and is quasihermetic.
• This arrangement can be used, for example, in short-pulse lasers.
• the connection to the carrier substrate can also be carried out by an adhesive bond.
• Fig. 4 also shows a component arrangement without a cover substrate. In this embodiment, not only the space 1 a expires, but the entire component "overmolded".
• Fig. 5 shows an arrangement of a side emitting component in, for example, a ceramic package.
• a single anisotropically etched silicon component 50 is provided in the space 1 a, which serves as a mirror element for Umienkung of the beam.
• This type of arrangement can also be provided for classic TO housing.
• FIG. 6 shows a plan view of the anisotropically etched structure of a mirror frame 60.
• a breakthrough 61 in the silicon due to the inclination of the crystal is trapezoidal, both in the region of an upper opening 61a and in the region of a lower opening 61b, and axially symmetric in one direction ,
• the corner angles on the longer side with the 45 degree mirror plane are approximately 83.2 degrees each. At the opposite shorter side, the angles are approximately 96.8 degrees.
• Edges of the upper and lower openings 61 a, 61 b extend in pairs parallel to each other.
• FIG. 7a shows a plan view of an anisotropically etched structure of a mirror frame 70.
• a masking opening for the anisotropic etching process is not selected in this case along the trapezoidally shaped 111 crystal planes (see FIG. 6), but formed with a compensation structure.
• This has the consequence that the breakthrough 71, the upper opening 71 a of the etching pit (in contrast to the lower opening 71 b) in comparison to Fig. 6 is not completely pronounced as a trapezoid, but limited in a direction of their extension becomes. In this way it is possible to reduce the lateral dimension of the aperture 71 and thus to arrange a larger number of etched structures on the silicon substrate.
• different compensation structures can be displayed.
• Fig. 7b shows a top view of another anisotropically etched structure of a mirror frame 70.
• the same reference numerals are used in Fig. 7b as in Fig. 7a.
• the illustration relates to an embodiment of the etched silicon component, wherein the size and shape of the masking opening are chosen so that the trapezoid formed for the lower opening 71 b (as well as for the upper opening 71 a) not over the entire width of Breakthrough 71 extends, but substantially over a width of at least 2/3 of the total width of the opening.
• the array 80 shows an arrangement of a plurality of openings in the form of an array 80.
• a plurality of components can be encapsulated simultaneously in terms of usefulness, thus increasing, for example, the light output of the component arrangement in a space-saving manner. This is particularly advantageous for systems with high light output.
• the array 80 may be embodied both as a benefit of pure spacers 3 with a 45 degree mirror surface or also in combination with a top substrate as a benefit of 45 degree mirror surface encapsulants.
• Fig. 9 shows a circumferential spacer 3, which is designed as an anisotropically etched silicon component, with a 45 degree mirror surface.
• the spacer 3 is designed such that a light beam can emerge from the package in the center or can enter ("center e ission").
• Such spacers 3 can likewise be designed with a cover substrate as encapsulation (cf. FIG. 10).
• FIG. 10 shows a semifinished product consisting of a spacer 3, which is embodied as an anisotropically etched silicon component with a 45-degree mirror surface and cover substrate.
• a structured bonding surface may be provided, for example a metallization.
• Fig. 11 shows an arrangement in which a silicon element with 45 degree mirror surface is used for coupling to a waveguide, for example a glass fiber. In this way, light can be coupled out of the package or coupled into another waveguide (deflection of a signal).
• Fig. 12 shows an arrangement of a side-emitting device, for example a laser diode or an LED, for example in a ceramic package.
• a side-emitting device for example a laser diode or an LED, for example in a ceramic package.
• the placement of a plurality of silicon elements with 45 degree mirror surfaces is provided. This is advantageous when the side-emitting component emits light laterally in several directions. Laterally emerging light beams of one direction can, for example, also be provided for carrying out a calibration of the laser diode via a further monitor photodiode installed in the pack.
• FIG. 13 shows an arrangement in which components 130, 131 are arranged in adjacent and separately formed installation spaces 132, 133.
• the Hau is sung solution of the components 130, 131 made in the wafer level.
• a carrier substance may be provided, for example, of silicon.
• the carrier substrate 1 made of silicon is prepared with plated-through holes 7.
• the plated-through holes 7 can be realized for example by dry or wet etching with subsequent metal filling of the holes by a galvanic process.
• contacts for one component are provided on a front side of the carrier substrate and contacts for later assembly in SMD construction are provided on the rear side.
• the carrier substrate 1 made of silicon Before the galvanic deposition and the generation of the contacts by an inorganic layer, a thermal oxidation of the silicon, the deposition of, for example, a nitride layer in an LPCVD process or other CVD processes ⁇ eg PECVD plasma-enhanced CVD) for the deposition of insulating layers is conceivable.
• an electrically conductive "seed" layer Before the galvanic deposition of the metal filling of the vias, an electrically conductive "seed" layer must be applied to the previously deposited passivation layer, for example by sputtering processes.
• a multiplicity of components are first mounted serially onto a prepared carrier substrate 1, which may be in the form of a wafer or in the form of a rectangular utility, and added in a further step by the application of a cap wafer or cap array in the wafer level or as a benefit.
• a plurality of encapsulated components is formed at the same time.
• the individual packages are then created by separating the composite.
• Fig. 14 shows an arrangement in which the spacer 3 made of silicon of a 100 orientation unsatisfactory single crystal has been manufactured by anisotropic wet chemical etching. As a result, the 1 1 crystal planes are all pronounced at an angle of about 54.7 degrees. In this embodiment, the upward light emission from the package is favored in several directions.
• the production is as previously described in Fig. 13 be written as a housework by means of wafer-level packaging.
• FIG. 15 shows an arrangement in which the spacer 3 and the carrier substrate 1 are manufactured completely in one piece from silicon.
• a cavity is etched on the front side into the silicon substrate by means of anisotropic wet-chemical structuring. This cavity is connected at the back with dry etched through contacts.
• the silicon substrate 1 is electrically insulated as described for FIG.
• FIG. 16 shows an arrangement in which the spacer 3 and the carrier substrate 1 are completely manufactured in one piece from silicon.
• a cavity is etched on the front side into the silicon substrate by means of anisotropic wet-chemical structuring.
• This cavity is connected at the back with through contacts 7, which are produced in comparison to FIG. 15 by means of anisotropic wet-chemical etching.
• the silicon substrate 1 is electrically isolated as described in FIG.
• FIG. 17 shows an arrangement in which the installation space has first been etched approximately perpendicularly by means of dry etching. In a subsequent wet-chemical anisotropic etching step then a 45 degree surface is formed, which is useful as a mirror plane.
• This construction has the advantage that due to the combination of different etching processes, the surface coverage on a substrate can be further increased.
• Fig. 18 shows a component, on which on the cover substrate 4, a Linsenanord ⁇ voltage is additionally arranged 180th
• FIG. 1 shows a schematic representation of a component arrangement in which a mirror plane of 45 degrees is provided on the circumferential spacer 3 (silicon frame).
• Another element 190 which is designed as an anisotropically etched silicon component, with an inclined surface 191, also 45 degrees, is arranged before mounting the cap on the Trä gersubstrat 1 on the same.
• the inclined surface 191 a light-reflecting surface is provided, which in the embodiment shown has a reflective coating 191a.
• FIG. 20 shows a schematic representation of a component arrangement in which a lower opening 200 in the spacer 3, which is used as an anisotropically etched silicon component. is executed, with a chamfer 201 is executed, which is directed in the example shown substantially vertically out.
• this has the advantage of reducing the installation space 1a and thus the overall size of the package, on the other hand it is thus possible to arrange a side-emmembering component closer to the light-reflecting mirror surface. This favors the impact of a light beam, which has been widened by possible beam divergence, on the mirror surface provided. In this way, light emerging laterally from the component can be guided even more favorably out of the installation space 1a and the component height additionally reduced.
• the chamfer 201 is realized on the lower opening 200 of the spacer 3, for example by a dry etching process.
• it can also be provided to achieve the chamfer 201 by wet-chemical overetching of the spacer 3, since in the anisotropic etching process at substantially convex edges of the spacer 3 made of silicon substantially perpendicular crystal planes with respect to 100 orientation.
• FIG. 21 shows a schematic representation of a component arrangement in which a lower opening 210 in the spacer 3, which is embodied as an anisotropically etched silicon component, is designed with an undercut 211 relative to the surface of the spacer 3.
• the undercut 21 1 can on the one hand as shown in FIG. 20 achieved by suitable dry etching the who, on the other hand a wet-chemical anisotropic etching of the back of the spacer 3 is provided, in which the opening and thus the undercut 211 are predetermined by a corresponding masking.

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• 2018
  • 2018-02-09 DE DE102018102961.6A patent/DE102018102961A1/de active Pending
• 2019
  • 2019-02-11 KR KR1020207025664A patent/KR20200117000A/ko not_active Application Discontinuation
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