Classifications

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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
  • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
  • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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  • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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  • H01L2224/321—Disposition
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  • H01L2224/732—Location after the connecting process
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  • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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  • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
  • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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Definitions

• the present invention relates to an electronic system adapted to be attached to a printed circuit, the printed circuit can then be mounted in an electronic device, for example, a smart phone.
• an electronic system may comprise several electronic chips which are mounted in a box to form an interface between the electronic chips and the printed circuit, known to those skilled in the art under its English name "Printed Circuit Board” (PCB) .
• PCB printed Circuit Board
• the box has connection ports.
• the patent application US2016 / 0064342 discloses a system comprising an electronic chip, comprising connectors, which is positioned on a lower support with the connectors placed upwards.
• the lower bracket has metal connection ports.
• a metallic redistribution layer is placed on the connectors of the electronic chip to form a system. Through vias connect the redistribution layer to the connection ports to allow the system to form an interposer between a printed circuit and an auxiliary system.
• Such a system requires many steps of realization (creation of vias, etc.), which increases its cost.
• the redistribution layer has a large thickness and requires many preparation steps before it can be connected to the electronic chip, which has disadvantages.
• the invention relates to an electronic system comprising a front surface comprising connection ports, the electronic system comprising:
• each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component belonging to the front surface of the electronic system,
• connection ports and the plurality of three-dimensional interconnections being made during the same technical step in the same material metallic
• an encapsulation layer in particular, protecting the three-dimensional interconnections.
• the electronic components can be conveniently and losslessly connected to each other.
• the connection ports of the system are easily configurable and the system can be directly mounted on an integrated circuit.
• Such a system can advantageously receive electronic components of different types and connect them conveniently.
• the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation.
• the system comprises a plurality of vertically assembled electronic components to form a stack.
• all the connectors of the electronic components are connected to the connection ports optimally with a small footprint.
• the electronic component located at the bottom of the stack allows the heat to be evacuated directly from the electronic system.
• the electronic components have the same orientation in the stack.
• the electronic component comprises raised conductive pads on the connectors of said electronic component. Such elevation studs make it possible to vertically shift the connectors relative to the front surface of the electronic component. In other words, the conductive pads extend in vertical projection from the front surface of the electronic component.
• elevation pads make it possible to improve the compatibility with the interconnections or to offset the position of the connectors in order to limit the risk of interference between the three-dimensional interconnections and the electronic component.
• the reported elevation pads are formed prior to the step of making three-dimensional interconnection.
• the elevation pads make compatible the three-dimensional interconnections with the connectors of the electronic component by forming a compatible metal interface.
• the electronic system comprises:
• a first stack of electronic components forming a lower subsystem, the rear surface of an electronic component of which belongs to the front surface of the lower subsystem,
• an elevation redistribution layer formed between the lower subsystem and the upper subsystem so as to connect them.
• An overall electronic system formed of a plurality of subsystems which are vertically stacked together is advantageously formed.
• the elevation redistribution layer makes it possible to connect the connection ports of the lower subsystem with those of the upper subsystem.
• the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
• the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
• the invention also relates to a method for manufacturing an electronic system comprising:
• each electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite the front surface, the rear surface of the electronic component being positioned on the sacrificial element,
• a step of producing a plurality of three-dimensional interconnections made by metal deposition so as, on the one hand, to fill open areas of the sacrificial element to form the connection ports of the system and, on the other hand, forming a redistribution layer connecting the connectors of the electronic component to the connection ports of the system,
• the electronic components can be positioned accurately on the sacrificial element, which optimally form three-dimensional interconnections.
• the connection ports of the system are made conveniently accessible.
• the system can thus be directly mounted on an integrated circuit.
• Such a system can advantageously receive electronic components of different types and connect them conveniently.
• the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation.
• at least one connector and at least one connection port are separated by a vertical distance greater than 10 ⁇ , preferably greater than 40 ⁇ , and three-dimensionally interconnected.
• the vertical direction is defined orthogonally to the horizontal direction along which the sacrificial element extends.
• Such spacing imposes significant technical constraints for the interconnection.
• at least one interconnection has a shape ratio greater than 2.5: 1, preferably greater than 5: 1, more preferably greater than 10: 1 for a vertical distance of between 10 pm and 100 pm. Beyond a vertical distance of ⁇ ⁇ , this aspect ratio is greater than 1 .5: 1, preferably greater than 3: 1, more preferably greater than 6: 1. As a reminder, the aspect ratio corresponds to the vertical distance traversed by the interconnection over its width.
• a subtractive method as taught by US6774499B1 is not suitable for providing interconnection for such a large vertical distance and having a vertical distance to interconnect width ratio of greater than 2: 1.
• the method comprises a plurality of electronic component transfer steps and a plurality of three-dimensional redistribution layer production steps.
• the method comprises a step of depositing a passivation layer so as to cover the surface of the sacrificial element and the electronic component while maintaining the plurality of connectors of the electronic component and the zones of the sacrificial element for forming the connection ports of the system.
• the sacrificial element is in the form of an adhesive film, in particular, double-sided.
• an adhesive film in particular, double-sided.
• a sacrificial element is simple to manipulate for an operator.
• a double-sided adhesive film secures the support and the electronic components together temporarily during the production of the system.
• the sacrificial element is in the form of an adhesive resin layer.
• the sacrificial element is in the form of a non-adhesive polymer layer. More preferably, the sacrificial element is configured to lose its adhesion characteristics from a predetermined temperature. Such a sacrificial element can be conveniently removed without mechanical action that can damage the system being made. Preferably, the sacrificial element loses its adhesion characteristics from a temperature below 250 ° C, which avoids damage to the system during heating.
• the sacrificial element is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
• a BrewerBond® sacrificial element from Brewer Science, 3M WSS® or Sekisui's "SELFA" is particularly suitable.
• the sacrificial element is selected from the following set of: “ZoneBond” ®, “BrewerBond” ® and “WaferBond” ® from Brewer Science, “WSS” ® from 3M, “SELFA” ® from Sekisui and “ Revalpha® from Nitto.
• Such sacrificial elements have optimal characteristics for a reduced cost. It goes without saying that other trade names of other companies may also be appropriate.
• the sacrificial element allows the electronic system to take off by mechanical action without deterioration.
• a sacrificial element of the type "TM-X12" ® of Hitachi Chemicals is particularly suitable.
• the method comprises a step of making an opening in the system so as to discover the front face of at least one electronic component having a sensor function.
• the method is compatible for the realization of a system having a sensor function.
• the method comprises at least two steps of depositing a passivation layer in order to protect the interconnections in the system.
• the method comprises at least two steps of producing a plurality of three-dimensional interconnections in order to form a plurality of superimposed redistribution layers. Complex redistributions can then be carried out in a practical way.
• the method comprises a step of producing a plurality of three-dimensional interconnections made by metal deposition on top of an electronic component to form an upper redistribution layer connected to connectors of said electronic component.
• the upper surface and the lower surface of the component allow interconnection of the same type, which facilitates the mounting of the system in a dense environment.
• the method comprises a step of deposition of at least one electronic component on the upper redistribution layer, each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned opposite the upper redistribution layer.
• Stacks of components can thus be mounted in stages thanks to the presence of the upper redistribution layer which makes it possible to offer easily accessible connection ports for connecting two different stacks.
• very complex systems can be formed.
• the method comprises a step of forming a three-dimensional passive component during the step of producing a plurality of three-dimensional interconnections.
• a three-dimensional passive component is preferably made in a single step, which accelerates the realization of the system.
• the method comprises a step of depositing a metal layer on the rear surface of at least one electronic component so as to improve the heat dissipation.
• the method comprises a step of depositing at least two electronic components superimposed on the sacrificial element and a step of connecting the connectors of said electronic components during the step of producing a plurality of three-dimensional interconnections.
• Complex assemblies can advantageously be made in a system.
• an electronic system comprising heterogeneous electronic components based on three-dimensional interconnections is produced in a practical and inexpensive manner.
• Advantage is thus advantageously taken of the vertical dimension to increase the integration density.
• optimal heat dissipation is provided via the direct contact between the rear face of the active components and the printed circuit (including a motherboard) on which the system is welded.
• FIGS. 1A-1G are diagrammatic representations of steps for producing a system according to the invention.
• FIG. 2 is a schematic representation of an electronic component
• FIG. 3 is a schematic representation of a system according to the invention integral with an integrated circuit
• Figures 4 and 5 show a system according to the invention in section ( Figure 4) and in a view from below ( Figure 5) with a distribution of the connection ports
• Figure 6 is a schematic representation of a system with balls reported connections
• FIG. 7 is a schematic representation of a system with a dissipation metal layer
• FIG. 8 is a schematic representation of a system with two passivation layers
• FIG. 9 is a schematic representation of a system with two metal layers of three-dimensional interconnections
• FIG. 10 is a schematic representation of a system with an access opening to an electronic component having a sensor function
• FIGS. 11 and 12 show a system comprising a surface-mounted component
• FIG. 13 represents a system comprising a three-dimensional passive component
• Figures 14, 15 and 16 show several embodiments of systems having a redistribution layer placed in the upper part so as to connect to other electronic components.
• an electronic system comprising a plurality of electronic components adapted to be mounted on a printed circuit to form an electronic card.
• Such an electronic card can be mounted in all kinds of electronic devices, for example, a computer, a watch, a smart phone, a connected object, a garment, a portable equipment, etc.
• a "system in package” system is formed which comprises several electronic components.
• a system of the QFN or LGA type whose connection ports extend in the same plane in the continuity of said system, that is to say, without to be protruding.
• FIG. 1A there is shown a step of applying a sacrificial element 2 to a support piece 1.
• the support part 1 is in the form of a flat surface based on silicon, glass, ceramic, metal, organic materials or any type of material suitable for use as a support.
• the support part 1 is preferably circular or rectangular, but it goes without saying that other shapes could be suitable.
• the support surface is greater than 2000 mm 2.
• the sacrificial element 2 has a dual function. It makes it possible, on the one hand, to accurately and robustly position the electronic components 3 of the system during its production and, on the other hand, to be able to release them when the system is made. In other words, the sacrificial element 2 forms a temporary support for the electronic components 3 so that they are integrated in the system S.
• the sacrificial element 2 is in the form of a layer which is organic, inorganic, polymeric or metallic.
• the sacrificial element 2 may be deposited by centrifugal coating, by spraying, by lamination, by pressing, by growth or the like.
• the sacrificial element 2 is in the form of an adhesive film which is easy to handle, in particular double-sided.
• the sacrificial element 2 is configured to lose its adhesion characteristics from a predetermined temperature.
• a sacrificial element 2 of the "Revalpha" ® type from Nitto is particularly suitable.
• the sacrificial element 2 is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element 2 converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
• a sacrificial element 2 of the "BrewerBond” ® type of Brewer Science or “WSS” ® of 3M or “SELFA” ® of Sekisui is particularly suitable. More preferably, the sacrificial element 2 allows takeoff of the system by mechanical action without deterioration. For this purpose, a sacrificial element 2 of the "TM-X12" type of Hitachi Chemicals is particularly suitable.
• each electronic component 3 has a front surface 3A having a plurality of connectors 30 and a rear surface 3B opposite to the front surface 3A.
• the rear surface 3B of each electronic component 3 is devoid of connectors 30.
• two electronic components 3 are positioned directly in contact with the sacrificial element 2 and are designated electronic components of rank 1.
• Other electronic components can be positioned in superposition on the electronic components 3 of rank 1, these electronic components 3 being designated electronic components of rank 2.
• the component 3 superimposed electronic has a rank n + 1.
• an electronic component of rank 2 is positioned on one of the electronic components of rank 1.
• the rear surface 3B of the electronic components 3 of rank 1 is positioned on the sacrificial element 2 so as to extend at the front surface of the electronic system S to remove the heat optimally.
• the positioning of the electronic components 3 is preferably performed by a so-called "pick and place” transfer method.
• the sacrificial element 2 is adhesive, the electronic components 3 of rank 1 are stable on the sacrificial element 2.
• an adhesive layer can be added between the electronic components 3 and the sacrificial element 2.
• a layer of adhesive is applied between two superimposed electronic components 3.
• the adhesive layer is deposited between the rear surface 3B of the electronic component 3 of higher rank and the front surface 3A of the electronic component 3 of lower rank. Precise positioning ensures optimum interconnection.
• the total vertical thickness (electronic component (s) 3 and glue layer (s)) is greater than 1 ⁇ , more particularly greater than 40 ⁇ .
• the flanks of the electronic components 3 can be straight, undercut and / or undercut. For the sake of clarity, only electronic components 3 having straight flanks have been used in the figures.
• FIG. 1C there is shown a step of depositing a passivation layer 4 so as to cover the surface of the sacrificial element 2 and the front surface 3A of the electronic component 3 while forming openings 40 now discovered the plurality of connectors 30 of the electronic component 3 and the areas of the sacrificial element 2 so as to form connection ports.
• the passivation layer 4 is deposited in a manner conforming or in a manner to adapt the angle of the flanks of the electronic components 3.
• the passivation layer 4 can be composed of an organic or inorganic material , such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It may be deposited by centrifugal coating, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposit known to those skilled in the art.
• openings 40 are made in the passivation layer 4, in order to discover the connectors 30 of the electronic components 3 and the zones of the sacrificial element 2.
• the openings 40 are made to using a photolithography process or using wet and / or dry chemical etching, plasma or laser etching. In a preferred manner, photosensitive materials are preferred in view of the advantages offered by the photolithography processes.
• the deposition of the passivation layer 4 may not be applied, thus reducing the time and cost of manufacture.
• the electronic system S comprises several electronic components 3 assembled vertically to form a stack.
• the electronic components 3 have the same orientation in the stack.
• the rear surface 3B of the electronic component 3 of higher rank is mounted on the front surface 3A of the electronic component 3 of lower rank.
• the electronic system S could comprise a stack of a large number of electronic components 3 of different natures.
• each electronic component 3 of higher rank of a stack has dimensions smaller than the electronic component 3 of lower rank so as to form a stack facilitating the formation of three-dimensional interconnections 5 between the various electronic components 3.
• the compactness and the integration density is thus increased in a practical way.
• the stack is pyramidal or walking stairs. According to the latter case, it is possible to stack electronic components 3 having an identical size or electronic components 3 of larger size over smaller electronic components 3. It goes without saying that the electronic components 3 may have different dimensions.
• connection ports 50 there is shown a step of producing a plurality of three-dimensional interconnections 5 made by metal deposition so as to connect the exposed zones 40 of the sacrificial element 2 to the connectors 30 of the electronic component 3, the filled areas of the sacrificial element 2 forming connection ports 50.
• the three-dimensional interconnections 5 and connection ports 50 are formed to interconnect the connectors 30 of the electronic components 3.
• the three-dimensional interconnections 5 are known per se, in particular by the patent application FR2965659.
• the method comprises:
• This metal layer can be composed of one or more electrically conductive materials and / or semiconductors.
• the thickness of the photoresist layer may vary from 20 to 700 ⁇ m and the aspect ratio (resolution) from 0.5: 1 to 50: 1.
• a step of depositing a metal layer by electrolysis or any other metal growth technique may be a step of depositing a metal layer by electrolysis or any other metal growth technique.
• the deposited metal may be copper, gold, silver, nickel, a metal alloy, or any other electrically conductive material.
• connection ports 50 of the system S and the connectors 30 of the electronic components 3 are respectively interconnected by the redistribution layer formed by the three-dimensional interconnections 5 made by metal deposition.
• the connection ports 50 are formed simultaneously with said three-dimensional interconnections 5.
• the three-dimensional interconnections 5 are made in one and the same step, which provides a gain of important time.
• the number of connectors 30 connected to each other depends on the degree of interaction between the two electronic components 3 in the electronic system S.
• the planar redistribution layer makes it possible to improve the routing between the electronic components 3, in particular in case of strong density of connectors 30.
• an encapsulation step 6 is represented so as to encapsulate the electronic components 3 and the interconnects 5.
• the encapsulation layer 6 is made of polymer, for example epoxy, and loaded or not with particles such as silica, alumina, etc. but it goes without saying that other similar materials might be suitable.
• the encapsulation step is performed by screen printing, injection molding, transfer or by pressure. Such an encapsulation layer 6 advantageously makes it possible to improve the mechanical robustness as well as the reliability of the electronic system S.
• FIG. 1F there is shown a step of separating the systems S from the sacrificial element 2. The separation step depends on the nature of the sacrificial element 2.
• the separation step can be performed by dissolution or etching, by sliding or by deactivating the sacrificial element 2 by means of a laser, UV or by heating it as in the case of "Revalpha" ® by Nitto.
• the assembly is heated to a temperature between 120 ° C and 250 ° C depending on the sacrificial element 2 used, which does not damage the system S.
• FIG 1 G it is shown a cutting step so as to separate the electronic systems S so that they can be used individually.
• a system S is in the form of a QFN-type box having flat connection ports 50.
• an electronic system S is thus obtained that can be secured to a printed circuit board 9 by various techniques, in particular by soldering the connection ports 50 of the electronic system S to the connection ports 90 of the printed circuit board 9. Bonding can be carried out with tin, alloys or conductive or insulating glues.
• connection ports 50 when the applications require a large number of inputs / outputs, the system S can integrate a plurality of connection ports 50 arranged on its periphery.
• the interconnections make it possible to form an optimal redistribution layer, on the one hand, between the connectors 30 and, on the other hand, between the connectors 30 and the connection ports 50.
• the number of Rows of connection ports 50 is not limited by comparison to a conventional QFN package.
• the system S may comprise conductive balls 150 secured to the connection ports 50 of the system S to connect to a printed circuit 9.
• conductive balls 150 are known to the person skilled in the art under their English designation "micro-bump" and will not be presented in detail.
• a metal layer 91 may be applied to the rear surface 3B of the electronic components 3. This metal layer 91 may be applied before the transfer of the electronic components 3 to the element sacrificial 2 or after the encapsulation step.
• a second passivation layer 4 ' may be applied after the completion of the interconnections 5 and before the encapsulation step.
• the deposition steps of the passivation layers 4, 4 'and deposition of the three-dimensional interconnections 5, 5' can be repeated to meet the need for integration of high-level S systems. density.
• superimposed redistribution layers are formed to allow complex links between a large number of connectors 30 and a large number of connection ports 50. This is particularly advantageous for routing a very large number of inputs / outputs, to integrate separately power supply levels or to incorporate a shield protecting the circuit from electromagnetic and electrostatic interference, etc.
• an opening 60 is made in the system S so that the front face 3A of the electronic component 3, having a sensor function, is uncovered.
• This opening 60 may be created during the encapsulation step, in particular by "transfer molding” or after encapsulation by locally etching the encapsulation layer or using other techniques known to those skilled in the art.
• the electronic system S comprises an additional electronic element XI, for example a component of the "Surface-Mounted Compound” type, which can be positioned in the system S after the realization of the three-dimensional interconnections 5 (FIG. 1 1) or before the realization of the three-dimensional interconnections 5 ( Figure 12).
• the additional electronic element XI is thus disposed next to the stack of the electronic components 3. The losses are then reduced.
• the additional electronic element XI is secured before the realization of the three-dimensional interconnections 5, it is the three-dimensional interconnections 5 that make the connection possible, which limits the number of manufacturing steps of the system S.
• the electronic system S comprises one or more three-dimensional passive components X2 which are preferably produced simultaneously with the interconnections three-dimensional 5. The losses are then reduced and the manufacture quick and easy.
• the electronic component comprises raised conductive pads reported on the connectors 30 of said electronic component 3.
• Such elevation pads are used to vertically shift the connectors 30 relative to the front surface 3A of the electronic component 3.
• the conductive pads extend in vertical projection from the front surface 3A of the electronic component 3.
• the reported elevation pads are formed prior to the three-dimensional interconnection realization step.
• the elevation pads make it possible to make the three-dimensional interconnections 5 compatible with the connectors 30 of the electronic component 3 by forming a compatible metal interface.
• FIGS. 14 to 15 there are shown several embodiments of systems S comprising an upper redistribution layer 5 "created on one or more electronic components 3 of the system S so as to allow the assembly additional electronic components on the upper face of the system S.
• the upper redistribution layer 5 "is planar is made during the same step of realization as the plurality of three-dimensional interconnections 5 as previously presented.
• the system S comprises an upper redistribution layer 5 "created above the electronic components 3 to allow the positioning of conductive balls 150".
• Such conductive balls 150 "allow connection to other electronic components or to an integrated circuit.Through the upper redistribution layer 5", the conductive balls 150 "can be placed at the desired locations on the upper surface of the system S.
• the system S comprises an upper redistribution layer 5 "created above the electronic components 3 on which a first electronic component X3 is mounted via conductive balls 150" and a second electronic component X4. via micro-welded wires.
• a mixed vertical integration can be achieved, which offers great design flexibility.
• the additional electronic components can be protected by an encapsulation layer, which provides mechanical and chemical protection of said additional components. This encapsulation can be performed simultaneously with the deposition of the encapsulation layer 6 of the system S or separately after encapsulation of said system S.
• a system S may be made comprising a plurality of subsystems SS1, SS2 separated by one or more elevation redistribution layers 5 ".
• Elevation redistribution layer 5 "' is created between a lower subsystem SS1 comprising one or more electronic components 3 and an upper subsystem SS2 comprising one or more electronic components 3.
• the redistribution layer of elevation 5 makes it possible to form an electronic system S comprising a stack of subsystems SS1, SS2, each comprising a stack of electronic components 3 as presented above, advantageously the elevation redistribution layer 5''fulfills the function of the sacrificial element 2 when it is desired to form an upper subsystem SS2 on a lower subsystem SSl.
• the lower subsystem SS1 is formed as previously taught with reference to FIG. 1, then the elevation redistribution layer 5 "'is formed and the upper subsystem SS2 is formed using the redistribution layer of FIG. elevation 5 "'in place of the sacrificial element 2.
• An electronic system S in elevation called" Build-up is thus formed.
• the elevation redistribution layer 5 "' can be carried out in one or more steps, in this example it is carried out in a first step of three-dimensional interconnection realization and a second step of realization of a planar redistribution layer.
• the elevation redistribution layer 5 "' is larger than the surface of the highest electronic component 3 of the lower subsystem SS1 so as to cooperate optimally with the lowest electronic component of the sub-system. superior system SS2.
• the elevation redistribution layer 5 advantageousously makes it possible to form the bond between the layers
• a passivation layer is deposited below and / or above the redistribution layer.
• elevation 5 "' Openings are made in this layer to provide the electrical connections between the three-dimensional interconnects 5 and the elevation redistribution layer 5 "'.
• the method of manufacture requires only a small number of technological steps to achieve multiple electronic systems S simultaneously, which reduces the time and cost of manufacture.
• the topology can be optimized to improve the electrical and thermal performance and to meet the needs of applications with a large number of inputs / outputs and / or incorporating sensors.
• the three-dimensional integration, using a single layer of metallization or by integrating several layers of metal, provides optimal miniaturization without degrading the functions.
• the various exemplary embodiments have been described for electronic components in the form of electronic chips. Nevertheless, it is recalled that other types of electronic components may be suitable.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
• Manufacturing Of Electrical Connectors (AREA)

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• 2017
  • 2017-08-08 FR FR1757587A patent/FR3070090B1/fr active Active
• 2018
  • 2018-08-08 WO PCT/EP2018/071513 patent/WO2019030286A1/fr unknown
  • 2018-08-08 EP EP18748941.4A patent/EP3665719A1/de active Pending

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