EP3665719A1 - Electronic system and method for the production of an electronic system using a sacrificial member - Google Patents

Electronic system and method for the production of an electronic system using a sacrificial member

Info

Publication number
EP3665719A1
EP3665719A1 EP18748941.4A EP18748941A EP3665719A1 EP 3665719 A1 EP3665719 A1 EP 3665719A1 EP 18748941 A EP18748941 A EP 18748941A EP 3665719 A1 EP3665719 A1 EP 3665719A1
Authority
EP
European Patent Office
Prior art keywords
electronic
sacrificial element
electronic component
electronic components
connectors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18748941.4A
Other languages
German (de)
French (fr)
Inventor
Ayad Ghannam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3dis Technologies
Original Assignee
3dis Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3dis Technologies filed Critical 3dis Technologies
Publication of EP3665719A1 publication Critical patent/EP3665719A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Definitions

  • the present invention relates to an electronic system adapted to be attached to a printed circuit, the printed circuit can then be mounted in an electronic device, for example, a smart phone.
  • an electronic system may comprise several electronic chips which are mounted in a box to form an interface between the electronic chips and the printed circuit, known to those skilled in the art under its English name "Printed Circuit Board” (PCB) .
  • PCB printed Circuit Board
  • the box has connection ports.
  • the patent application US2016 / 0064342 discloses a system comprising an electronic chip, comprising connectors, which is positioned on a lower support with the connectors placed upwards.
  • the lower bracket has metal connection ports.
  • a metallic redistribution layer is placed on the connectors of the electronic chip to form a system. Through vias connect the redistribution layer to the connection ports to allow the system to form an interposer between a printed circuit and an auxiliary system.
  • Such a system requires many steps of realization (creation of vias, etc.), which increases its cost.
  • the redistribution layer has a large thickness and requires many preparation steps before it can be connected to the electronic chip, which has disadvantages.
  • the invention relates to an electronic system comprising a front surface comprising connection ports, the electronic system comprising:
  • each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component belonging to the front surface of the electronic system,
  • connection ports and the plurality of three-dimensional interconnections being made during the same technical step in the same material metallic
  • an encapsulation layer in particular, protecting the three-dimensional interconnections.
  • the electronic components can be conveniently and losslessly connected to each other.
  • the connection ports of the system are easily configurable and the system can be directly mounted on an integrated circuit.
  • Such a system can advantageously receive electronic components of different types and connect them conveniently.
  • the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation.
  • the system comprises a plurality of vertically assembled electronic components to form a stack.
  • all the connectors of the electronic components are connected to the connection ports optimally with a small footprint.
  • the electronic component located at the bottom of the stack allows the heat to be evacuated directly from the electronic system.
  • the electronic components have the same orientation in the stack.
  • the electronic component comprises raised conductive pads on the connectors of said electronic component. Such elevation studs make it possible to vertically shift the connectors relative to the front surface of the electronic component. In other words, the conductive pads extend in vertical projection from the front surface of the electronic component.
  • elevation pads make it possible to improve the compatibility with the interconnections or to offset the position of the connectors in order to limit the risk of interference between the three-dimensional interconnections and the electronic component.
  • the reported elevation pads are formed prior to the step of making three-dimensional interconnection.
  • the elevation pads make compatible the three-dimensional interconnections with the connectors of the electronic component by forming a compatible metal interface.
  • the electronic system comprises:
  • a first stack of electronic components forming a lower subsystem, the rear surface of an electronic component of which belongs to the front surface of the lower subsystem,
  • an elevation redistribution layer formed between the lower subsystem and the upper subsystem so as to connect them.
  • An overall electronic system formed of a plurality of subsystems which are vertically stacked together is advantageously formed.
  • the elevation redistribution layer makes it possible to connect the connection ports of the lower subsystem with those of the upper subsystem.
  • the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
  • the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer.
  • the invention also relates to a method for manufacturing an electronic system comprising:
  • each electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite the front surface, the rear surface of the electronic component being positioned on the sacrificial element,
  • a step of producing a plurality of three-dimensional interconnections made by metal deposition so as, on the one hand, to fill open areas of the sacrificial element to form the connection ports of the system and, on the other hand, forming a redistribution layer connecting the connectors of the electronic component to the connection ports of the system,
  • the electronic components can be positioned accurately on the sacrificial element, which optimally form three-dimensional interconnections.
  • the connection ports of the system are made conveniently accessible.
  • the system can thus be directly mounted on an integrated circuit.
  • Such a system can advantageously receive electronic components of different types and connect them conveniently.
  • the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation.
  • at least one connector and at least one connection port are separated by a vertical distance greater than 10 ⁇ , preferably greater than 40 ⁇ , and three-dimensionally interconnected.
  • the vertical direction is defined orthogonally to the horizontal direction along which the sacrificial element extends.
  • Such spacing imposes significant technical constraints for the interconnection.
  • at least one interconnection has a shape ratio greater than 2.5: 1, preferably greater than 5: 1, more preferably greater than 10: 1 for a vertical distance of between 10 pm and 100 pm. Beyond a vertical distance of ⁇ ⁇ , this aspect ratio is greater than 1 .5: 1, preferably greater than 3: 1, more preferably greater than 6: 1. As a reminder, the aspect ratio corresponds to the vertical distance traversed by the interconnection over its width.
  • a subtractive method as taught by US6774499B1 is not suitable for providing interconnection for such a large vertical distance and having a vertical distance to interconnect width ratio of greater than 2: 1.
  • the method comprises a plurality of electronic component transfer steps and a plurality of three-dimensional redistribution layer production steps.
  • the method comprises a step of depositing a passivation layer so as to cover the surface of the sacrificial element and the electronic component while maintaining the plurality of connectors of the electronic component and the zones of the sacrificial element for forming the connection ports of the system.
  • the sacrificial element is in the form of an adhesive film, in particular, double-sided.
  • an adhesive film in particular, double-sided.
  • a sacrificial element is simple to manipulate for an operator.
  • a double-sided adhesive film secures the support and the electronic components together temporarily during the production of the system.
  • the sacrificial element is in the form of an adhesive resin layer.
  • the sacrificial element is in the form of a non-adhesive polymer layer. More preferably, the sacrificial element is configured to lose its adhesion characteristics from a predetermined temperature. Such a sacrificial element can be conveniently removed without mechanical action that can damage the system being made. Preferably, the sacrificial element loses its adhesion characteristics from a temperature below 250 ° C, which avoids damage to the system during heating.
  • the sacrificial element is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
  • a BrewerBond® sacrificial element from Brewer Science, 3M WSS® or Sekisui's "SELFA" is particularly suitable.
  • the sacrificial element is selected from the following set of: “ZoneBond” ®, “BrewerBond” ® and “WaferBond” ® from Brewer Science, “WSS” ® from 3M, “SELFA” ® from Sekisui and “ Revalpha® from Nitto.
  • Such sacrificial elements have optimal characteristics for a reduced cost. It goes without saying that other trade names of other companies may also be appropriate.
  • the sacrificial element allows the electronic system to take off by mechanical action without deterioration.
  • a sacrificial element of the type "TM-X12" ® of Hitachi Chemicals is particularly suitable.
  • the method comprises a step of making an opening in the system so as to discover the front face of at least one electronic component having a sensor function.
  • the method is compatible for the realization of a system having a sensor function.
  • the method comprises at least two steps of depositing a passivation layer in order to protect the interconnections in the system.
  • the method comprises at least two steps of producing a plurality of three-dimensional interconnections in order to form a plurality of superimposed redistribution layers. Complex redistributions can then be carried out in a practical way.
  • the method comprises a step of producing a plurality of three-dimensional interconnections made by metal deposition on top of an electronic component to form an upper redistribution layer connected to connectors of said electronic component.
  • the upper surface and the lower surface of the component allow interconnection of the same type, which facilitates the mounting of the system in a dense environment.
  • the method comprises a step of deposition of at least one electronic component on the upper redistribution layer, each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned opposite the upper redistribution layer.
  • Stacks of components can thus be mounted in stages thanks to the presence of the upper redistribution layer which makes it possible to offer easily accessible connection ports for connecting two different stacks.
  • very complex systems can be formed.
  • the method comprises a step of forming a three-dimensional passive component during the step of producing a plurality of three-dimensional interconnections.
  • a three-dimensional passive component is preferably made in a single step, which accelerates the realization of the system.
  • the method comprises a step of depositing a metal layer on the rear surface of at least one electronic component so as to improve the heat dissipation.
  • the method comprises a step of depositing at least two electronic components superimposed on the sacrificial element and a step of connecting the connectors of said electronic components during the step of producing a plurality of three-dimensional interconnections.
  • Complex assemblies can advantageously be made in a system.
  • an electronic system comprising heterogeneous electronic components based on three-dimensional interconnections is produced in a practical and inexpensive manner.
  • Advantage is thus advantageously taken of the vertical dimension to increase the integration density.
  • optimal heat dissipation is provided via the direct contact between the rear face of the active components and the printed circuit (including a motherboard) on which the system is welded.
  • FIGS. 1A-1G are diagrammatic representations of steps for producing a system according to the invention.
  • FIG. 2 is a schematic representation of an electronic component
  • FIG. 3 is a schematic representation of a system according to the invention integral with an integrated circuit
  • Figures 4 and 5 show a system according to the invention in section ( Figure 4) and in a view from below ( Figure 5) with a distribution of the connection ports
  • Figure 6 is a schematic representation of a system with balls reported connections
  • FIG. 7 is a schematic representation of a system with a dissipation metal layer
  • FIG. 8 is a schematic representation of a system with two passivation layers
  • FIG. 9 is a schematic representation of a system with two metal layers of three-dimensional interconnections
  • FIG. 10 is a schematic representation of a system with an access opening to an electronic component having a sensor function
  • FIGS. 11 and 12 show a system comprising a surface-mounted component
  • FIG. 13 represents a system comprising a three-dimensional passive component
  • Figures 14, 15 and 16 show several embodiments of systems having a redistribution layer placed in the upper part so as to connect to other electronic components.
  • an electronic system comprising a plurality of electronic components adapted to be mounted on a printed circuit to form an electronic card.
  • Such an electronic card can be mounted in all kinds of electronic devices, for example, a computer, a watch, a smart phone, a connected object, a garment, a portable equipment, etc.
  • a "system in package” system is formed which comprises several electronic components.
  • a system of the QFN or LGA type whose connection ports extend in the same plane in the continuity of said system, that is to say, without to be protruding.
  • FIG. 1A there is shown a step of applying a sacrificial element 2 to a support piece 1.
  • the support part 1 is in the form of a flat surface based on silicon, glass, ceramic, metal, organic materials or any type of material suitable for use as a support.
  • the support part 1 is preferably circular or rectangular, but it goes without saying that other shapes could be suitable.
  • the support surface is greater than 2000 mm 2.
  • the sacrificial element 2 has a dual function. It makes it possible, on the one hand, to accurately and robustly position the electronic components 3 of the system during its production and, on the other hand, to be able to release them when the system is made. In other words, the sacrificial element 2 forms a temporary support for the electronic components 3 so that they are integrated in the system S.
  • the sacrificial element 2 is in the form of a layer which is organic, inorganic, polymeric or metallic.
  • the sacrificial element 2 may be deposited by centrifugal coating, by spraying, by lamination, by pressing, by growth or the like.
  • the sacrificial element 2 is in the form of an adhesive film which is easy to handle, in particular double-sided.
  • the sacrificial element 2 is configured to lose its adhesion characteristics from a predetermined temperature.
  • a sacrificial element 2 of the "Revalpha" ® type from Nitto is particularly suitable.
  • the sacrificial element 2 is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element 2 converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics.
  • a sacrificial element 2 of the "BrewerBond” ® type of Brewer Science or “WSS” ® of 3M or “SELFA” ® of Sekisui is particularly suitable. More preferably, the sacrificial element 2 allows takeoff of the system by mechanical action without deterioration. For this purpose, a sacrificial element 2 of the "TM-X12" type of Hitachi Chemicals is particularly suitable.
  • each electronic component 3 has a front surface 3A having a plurality of connectors 30 and a rear surface 3B opposite to the front surface 3A.
  • the rear surface 3B of each electronic component 3 is devoid of connectors 30.
  • two electronic components 3 are positioned directly in contact with the sacrificial element 2 and are designated electronic components of rank 1.
  • Other electronic components can be positioned in superposition on the electronic components 3 of rank 1, these electronic components 3 being designated electronic components of rank 2.
  • the component 3 superimposed electronic has a rank n + 1.
  • an electronic component of rank 2 is positioned on one of the electronic components of rank 1.
  • the rear surface 3B of the electronic components 3 of rank 1 is positioned on the sacrificial element 2 so as to extend at the front surface of the electronic system S to remove the heat optimally.
  • the positioning of the electronic components 3 is preferably performed by a so-called "pick and place” transfer method.
  • the sacrificial element 2 is adhesive, the electronic components 3 of rank 1 are stable on the sacrificial element 2.
  • an adhesive layer can be added between the electronic components 3 and the sacrificial element 2.
  • a layer of adhesive is applied between two superimposed electronic components 3.
  • the adhesive layer is deposited between the rear surface 3B of the electronic component 3 of higher rank and the front surface 3A of the electronic component 3 of lower rank. Precise positioning ensures optimum interconnection.
  • the total vertical thickness (electronic component (s) 3 and glue layer (s)) is greater than 1 ⁇ , more particularly greater than 40 ⁇ .
  • the flanks of the electronic components 3 can be straight, undercut and / or undercut. For the sake of clarity, only electronic components 3 having straight flanks have been used in the figures.
  • FIG. 1C there is shown a step of depositing a passivation layer 4 so as to cover the surface of the sacrificial element 2 and the front surface 3A of the electronic component 3 while forming openings 40 now discovered the plurality of connectors 30 of the electronic component 3 and the areas of the sacrificial element 2 so as to form connection ports.
  • the passivation layer 4 is deposited in a manner conforming or in a manner to adapt the angle of the flanks of the electronic components 3.
  • the passivation layer 4 can be composed of an organic or inorganic material , such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It may be deposited by centrifugal coating, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposit known to those skilled in the art.
  • openings 40 are made in the passivation layer 4, in order to discover the connectors 30 of the electronic components 3 and the zones of the sacrificial element 2.
  • the openings 40 are made to using a photolithography process or using wet and / or dry chemical etching, plasma or laser etching. In a preferred manner, photosensitive materials are preferred in view of the advantages offered by the photolithography processes.
  • the deposition of the passivation layer 4 may not be applied, thus reducing the time and cost of manufacture.
  • the electronic system S comprises several electronic components 3 assembled vertically to form a stack.
  • the electronic components 3 have the same orientation in the stack.
  • the rear surface 3B of the electronic component 3 of higher rank is mounted on the front surface 3A of the electronic component 3 of lower rank.
  • the electronic system S could comprise a stack of a large number of electronic components 3 of different natures.
  • each electronic component 3 of higher rank of a stack has dimensions smaller than the electronic component 3 of lower rank so as to form a stack facilitating the formation of three-dimensional interconnections 5 between the various electronic components 3.
  • the compactness and the integration density is thus increased in a practical way.
  • the stack is pyramidal or walking stairs. According to the latter case, it is possible to stack electronic components 3 having an identical size or electronic components 3 of larger size over smaller electronic components 3. It goes without saying that the electronic components 3 may have different dimensions.
  • connection ports 50 there is shown a step of producing a plurality of three-dimensional interconnections 5 made by metal deposition so as to connect the exposed zones 40 of the sacrificial element 2 to the connectors 30 of the electronic component 3, the filled areas of the sacrificial element 2 forming connection ports 50.
  • the three-dimensional interconnections 5 and connection ports 50 are formed to interconnect the connectors 30 of the electronic components 3.
  • the three-dimensional interconnections 5 are known per se, in particular by the patent application FR2965659.
  • the method comprises:
  • This metal layer can be composed of one or more electrically conductive materials and / or semiconductors.
  • the thickness of the photoresist layer may vary from 20 to 700 ⁇ m and the aspect ratio (resolution) from 0.5: 1 to 50: 1.
  • a step of depositing a metal layer by electrolysis or any other metal growth technique may be a step of depositing a metal layer by electrolysis or any other metal growth technique.
  • the deposited metal may be copper, gold, silver, nickel, a metal alloy, or any other electrically conductive material.
  • connection ports 50 of the system S and the connectors 30 of the electronic components 3 are respectively interconnected by the redistribution layer formed by the three-dimensional interconnections 5 made by metal deposition.
  • the connection ports 50 are formed simultaneously with said three-dimensional interconnections 5.
  • the three-dimensional interconnections 5 are made in one and the same step, which provides a gain of important time.
  • the number of connectors 30 connected to each other depends on the degree of interaction between the two electronic components 3 in the electronic system S.
  • the planar redistribution layer makes it possible to improve the routing between the electronic components 3, in particular in case of strong density of connectors 30.
  • an encapsulation step 6 is represented so as to encapsulate the electronic components 3 and the interconnects 5.
  • the encapsulation layer 6 is made of polymer, for example epoxy, and loaded or not with particles such as silica, alumina, etc. but it goes without saying that other similar materials might be suitable.
  • the encapsulation step is performed by screen printing, injection molding, transfer or by pressure. Such an encapsulation layer 6 advantageously makes it possible to improve the mechanical robustness as well as the reliability of the electronic system S.
  • FIG. 1F there is shown a step of separating the systems S from the sacrificial element 2. The separation step depends on the nature of the sacrificial element 2.
  • the separation step can be performed by dissolution or etching, by sliding or by deactivating the sacrificial element 2 by means of a laser, UV or by heating it as in the case of "Revalpha" ® by Nitto.
  • the assembly is heated to a temperature between 120 ° C and 250 ° C depending on the sacrificial element 2 used, which does not damage the system S.
  • FIG 1 G it is shown a cutting step so as to separate the electronic systems S so that they can be used individually.
  • a system S is in the form of a QFN-type box having flat connection ports 50.
  • an electronic system S is thus obtained that can be secured to a printed circuit board 9 by various techniques, in particular by soldering the connection ports 50 of the electronic system S to the connection ports 90 of the printed circuit board 9. Bonding can be carried out with tin, alloys or conductive or insulating glues.
  • connection ports 50 when the applications require a large number of inputs / outputs, the system S can integrate a plurality of connection ports 50 arranged on its periphery.
  • the interconnections make it possible to form an optimal redistribution layer, on the one hand, between the connectors 30 and, on the other hand, between the connectors 30 and the connection ports 50.
  • the number of Rows of connection ports 50 is not limited by comparison to a conventional QFN package.
  • the system S may comprise conductive balls 150 secured to the connection ports 50 of the system S to connect to a printed circuit 9.
  • conductive balls 150 are known to the person skilled in the art under their English designation "micro-bump" and will not be presented in detail.
  • a metal layer 91 may be applied to the rear surface 3B of the electronic components 3. This metal layer 91 may be applied before the transfer of the electronic components 3 to the element sacrificial 2 or after the encapsulation step.
  • a second passivation layer 4 ' may be applied after the completion of the interconnections 5 and before the encapsulation step.
  • the deposition steps of the passivation layers 4, 4 'and deposition of the three-dimensional interconnections 5, 5' can be repeated to meet the need for integration of high-level S systems. density.
  • superimposed redistribution layers are formed to allow complex links between a large number of connectors 30 and a large number of connection ports 50. This is particularly advantageous for routing a very large number of inputs / outputs, to integrate separately power supply levels or to incorporate a shield protecting the circuit from electromagnetic and electrostatic interference, etc.
  • an opening 60 is made in the system S so that the front face 3A of the electronic component 3, having a sensor function, is uncovered.
  • This opening 60 may be created during the encapsulation step, in particular by "transfer molding” or after encapsulation by locally etching the encapsulation layer or using other techniques known to those skilled in the art.
  • the electronic system S comprises an additional electronic element XI, for example a component of the "Surface-Mounted Compound” type, which can be positioned in the system S after the realization of the three-dimensional interconnections 5 (FIG. 1 1) or before the realization of the three-dimensional interconnections 5 ( Figure 12).
  • the additional electronic element XI is thus disposed next to the stack of the electronic components 3. The losses are then reduced.
  • the additional electronic element XI is secured before the realization of the three-dimensional interconnections 5, it is the three-dimensional interconnections 5 that make the connection possible, which limits the number of manufacturing steps of the system S.
  • the electronic system S comprises one or more three-dimensional passive components X2 which are preferably produced simultaneously with the interconnections three-dimensional 5. The losses are then reduced and the manufacture quick and easy.
  • the electronic component comprises raised conductive pads reported on the connectors 30 of said electronic component 3.
  • Such elevation pads are used to vertically shift the connectors 30 relative to the front surface 3A of the electronic component 3.
  • the conductive pads extend in vertical projection from the front surface 3A of the electronic component 3.
  • the reported elevation pads are formed prior to the three-dimensional interconnection realization step.
  • the elevation pads make it possible to make the three-dimensional interconnections 5 compatible with the connectors 30 of the electronic component 3 by forming a compatible metal interface.
  • FIGS. 14 to 15 there are shown several embodiments of systems S comprising an upper redistribution layer 5 "created on one or more electronic components 3 of the system S so as to allow the assembly additional electronic components on the upper face of the system S.
  • the upper redistribution layer 5 "is planar is made during the same step of realization as the plurality of three-dimensional interconnections 5 as previously presented.
  • the system S comprises an upper redistribution layer 5 "created above the electronic components 3 to allow the positioning of conductive balls 150".
  • Such conductive balls 150 "allow connection to other electronic components or to an integrated circuit.Through the upper redistribution layer 5", the conductive balls 150 "can be placed at the desired locations on the upper surface of the system S.
  • the system S comprises an upper redistribution layer 5 "created above the electronic components 3 on which a first electronic component X3 is mounted via conductive balls 150" and a second electronic component X4. via micro-welded wires.
  • a mixed vertical integration can be achieved, which offers great design flexibility.
  • the additional electronic components can be protected by an encapsulation layer, which provides mechanical and chemical protection of said additional components. This encapsulation can be performed simultaneously with the deposition of the encapsulation layer 6 of the system S or separately after encapsulation of said system S.
  • a system S may be made comprising a plurality of subsystems SS1, SS2 separated by one or more elevation redistribution layers 5 ".
  • Elevation redistribution layer 5 "' is created between a lower subsystem SS1 comprising one or more electronic components 3 and an upper subsystem SS2 comprising one or more electronic components 3.
  • the redistribution layer of elevation 5 makes it possible to form an electronic system S comprising a stack of subsystems SS1, SS2, each comprising a stack of electronic components 3 as presented above, advantageously the elevation redistribution layer 5''fulfills the function of the sacrificial element 2 when it is desired to form an upper subsystem SS2 on a lower subsystem SSl.
  • the lower subsystem SS1 is formed as previously taught with reference to FIG. 1, then the elevation redistribution layer 5 "'is formed and the upper subsystem SS2 is formed using the redistribution layer of FIG. elevation 5 "'in place of the sacrificial element 2.
  • An electronic system S in elevation called" Build-up is thus formed.
  • the elevation redistribution layer 5 "' can be carried out in one or more steps, in this example it is carried out in a first step of three-dimensional interconnection realization and a second step of realization of a planar redistribution layer.
  • the elevation redistribution layer 5 "' is larger than the surface of the highest electronic component 3 of the lower subsystem SS1 so as to cooperate optimally with the lowest electronic component of the sub-system. superior system SS2.
  • the elevation redistribution layer 5 advantageousously makes it possible to form the bond between the layers
  • a passivation layer is deposited below and / or above the redistribution layer.
  • elevation 5 "' Openings are made in this layer to provide the electrical connections between the three-dimensional interconnects 5 and the elevation redistribution layer 5 "'.
  • the method of manufacture requires only a small number of technological steps to achieve multiple electronic systems S simultaneously, which reduces the time and cost of manufacture.
  • the topology can be optimized to improve the electrical and thermal performance and to meet the needs of applications with a large number of inputs / outputs and / or incorporating sensors.
  • the three-dimensional integration, using a single layer of metallization or by integrating several layers of metal, provides optimal miniaturization without degrading the functions.
  • the various exemplary embodiments have been described for electronic components in the form of electronic chips. Nevertheless, it is recalled that other types of electronic components may be suitable.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
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  • Manufacturing Of Electrical Connectors (AREA)

Abstract

The invention relates to a method for producing an electronic system (S), comprising: - a step of applying a sacrificial member (2) to a support piece (1); - a step of depositing at least one electronic component (3) on the sacrificial member (2); a step of producing a plurality of three-dimensional interconnect paths (5) in order to form the connection ports of the system (S) and to form a redistribution layer connecting the connectors (30) of the electronic component (3) to the connection ports of the system (S); an encapsulation step in order to protect the three-dimensional interconnect paths (5); and a step of separating the system (S) from the sacrificial member (2).

Description

SYSTEME ELECTRONIQUE ET PROCEDE DE FABRICATION D'UN SYSTEME ELECTRONIQUE PAR  ELECTRONIC SYSTEM AND METHOD FOR MANUFACTURING AN ELECTRONIC SYSTEM BY
UTILISATION D'UN ELEMENT SACRIFICIEL  USE OF A SACRIFICIAL ELEMENT
DOMAINE TECHNIQUE GENERAL ET ART ANTERIEUR  GENERAL TECHNICAL FIELD AND PRIOR ART
La présente invention concerne un système électronique adapté pour être fixé à un circuit imprimé, le circuit imprimé pouvant être ensuite monté dans un appareil électronique, par exemple, un téléphone intelligent. De manière connue, un système électronique peut comporter plusieurs puces électroniques qui sont montées dans un boitier pour former une interface entre les puces électroniques et le circuit imprimé, connu de l'homme du métier sous sa désignation anglaise « Printed Circuit Board » (PCB). A cet effet, le boitier comporte des ports de connexion. The present invention relates to an electronic system adapted to be attached to a printed circuit, the printed circuit can then be mounted in an electronic device, for example, a smart phone. In known manner, an electronic system may comprise several electronic chips which are mounted in a box to form an interface between the electronic chips and the printed circuit, known to those skilled in the art under its English name "Printed Circuit Board" (PCB) . For this purpose, the box has connection ports.
Afin de pouvoir améliorer les performances d'un tel système électronique, il est nécessaire de diminuer ou d'éliminer les éléments parasites générés par les connexions qui relient les différentes puces électroniques au boitier. A cet effet, il est souhaitable de réduire les longueurs électriques de ces connexions en réduisant la distance entre les puces et en miniaturisant le boiter. Aussi, il a été proposé d'empiler verticalement les puces électroniques dans un même boîtier afin de diminuer davantage les pertes. In order to be able to improve the performance of such an electronic system, it is necessary to reduce or eliminate the parasitic elements generated by the connections that connect the various electronic chips to the box. For this purpose, it is desirable to reduce the electrical lengths of these connections by reducing the distance between the chips and by miniaturizing the limp. Also, it has been proposed to vertically stack the electronic chips in the same housing to further reduce losses.
Cependant, cette miniaturisation est difficile à atteindre à cause des limitations des techniques actuelles d'assemblage. En effet, la plupart des techniques d'assemblage nécessitent de fabriquer un boitier, placer les puces électroniques dans le boitier, connecter lesdites puces électroniques au boîtier en utilisant des fils micro-soudés et à encapsuler l'ensemble pour le protéger de son environnement. L'utilisation de fils micro- soudés engendre de fortes pertes, ce qui présente un inconvénient. Lorsque l'on souhaite obtenir un système comportant un grand nombre de ports de connexion, il est souhaitable de prévoir une couche de redistribution qui permet de former une interface entre les ports de connexion du système et les connecteurs des composants électroniques. En particulier, lorsque la puce électronique comporte des connecteurs denses, c'est-à-dire très proches les uns des autres, une couche de redistribution permet d'écarter les ports de connexion du système afin de coopérer de manière optimale avec un circuit intégré. However, this miniaturization is difficult to achieve because of the limitations of current assembly techniques. Indeed, most assembly techniques require the manufacture of a housing, placing the electronic chips in the housing, connect said electronic chips to the housing using micro-welded son and encapsulate the assembly to protect it from its environment. The use of micro-welded son generates high losses, which has a disadvantage. When it is desired to obtain a system comprising a large number of connection ports, it is desirable to provide a redistribution layer which makes it possible to form an interface between the connection ports of the system and the connectors of the electronic components. In particular, when the electronic chip has dense connectors, that is to say very close to each other, a layer of redistribution allows to separate the connection ports of the system to cooperate optimally with an integrated circuit.
A cet effet, on connaît par la demande de brevet US2016/0064342, un système comportant une puce électronique, comportant des connecteurs, qui est positionnée sur un support inférieur avec les connecteurs placés vers le haut. Le support inférieur comporte des ports de connexion métallique. Une couche de redistribution métallique est placée sur les connecteurs de la puce électronique afin de former un système. Des vias traversants permettent de relier la couche de redistribution avec les ports de connexion afin de permettre au système de former un interposeur entre un circuit imprimé et un système auxiliaire. Un tel système nécessite de très nombreuses étapes de réalisation (création de vias, etc.), ce qui augmente son coût. En outre, la couche de redistribution présente une épaisseur importante et nécessite de nombreuses étapes de préparation avant de pouvoir être reliée à la puce électronique, ce qui présente des inconvénients. For this purpose, the patent application US2016 / 0064342 discloses a system comprising an electronic chip, comprising connectors, which is positioned on a lower support with the connectors placed upwards. The lower bracket has metal connection ports. A metallic redistribution layer is placed on the connectors of the electronic chip to form a system. Through vias connect the redistribution layer to the connection ports to allow the system to form an interposer between a printed circuit and an auxiliary system. Such a system requires many steps of realization (creation of vias, etc.), which increases its cost. In addition, the redistribution layer has a large thickness and requires many preparation steps before it can be connected to the electronic chip, which has disadvantages.
Par ailleurs, les composants et les systèmes électroniques nécessitent d'évacuer la chaleur qu'ils génèrent. Le boîtier joue un rôle très important dans la dissipation de cette chaleur puisqu'il permet de l'améliorer ou de la dégrader. On constate que les boîtiers qui utilisent les fils micro-soudés, tel que le QFN, disposent d'une excellente dissipation thermique mais des mauvaises performances électriques. En revanche, les boîtiers du type « flip-chip » affichent des meilleures performances électriques mais disposent d'une mauvaise dissipation thermique. II existe ainsi un besoin pour former un système électronique formant boîtier dont les ports de connexion sont reliés de manière optimale aux connecteurs des composants électroniques du système et qui permet une excellente dissipation thermique. In addition, components and electronic systems require the removal of the heat they generate. The housing plays a very important role in the dissipation of this heat since it can improve or degrade. It is found that the housings that use the micro-welded son, such as the QFN, have excellent heat dissipation but poor electrical performance. On the other hand, flip-chip type boxes display better electrical performance but have poor heat dissipation. There is thus a need to form an electronic housing system whose connection ports are optimally connected to the connectors of the electronic components of the system and which allows excellent heat dissipation.
On connaît dans l'art antérieur par le brevet US6774499B1 un système électronique comportant des ports de connexion réalisés en brasure, en palladium ou en or qui sont connectés postérieurement à des connecteurs d'un composant électronique par un dépôt métallique. Prior art is known in the US6774499B1 patent an electronic system comprising connection ports made of solder, palladium or gold which are subsequently connected to connectors of an electronic component by a metal deposit.
PRESENTATION GENERALE DE L'INVENTION A cet effet, l'invention concerne un système électronique comprenant une surface avant comprenant des ports de connexion, le système électronique comprenant : GENERAL PRESENTATION OF THE INVENTION To this end, the invention relates to an electronic system comprising a front surface comprising connection ports, the electronic system comprising:
- au moins un composant électronique, chaque composant électronique comportant une surface avant comportant une pluralité de connecteurs et une surface arrière opposée à la surface avant, la surface arrière du composant électronique appartenant à la surface avant du système électronique,  at least one electronic component, each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component belonging to the front surface of the electronic system,
- une pluralité d'interconnexions tridimensionnelles formant une couche de redistribution reliant les connecteurs du composant électronique aux ports de connexion du système, les ports de connexion et les pluralités d'interconnexions tridimensionnelles étant réalisée au cours d'une même étape technique dans un même matériau métallique, et  a plurality of three-dimensional interconnections forming a redistribution layer connecting the connectors of the electronic component to the connection ports of the system, the connection ports and the plurality of three-dimensional interconnections being made during the same technical step in the same material metallic, and
- une couche d'encapsulation, en particulier, protégeant les interconnexions tridimensionnelles.  an encapsulation layer, in particular, protecting the three-dimensional interconnections.
Grâce à l'invention, les composants électroniques peuvent être connectés de manière pratique et sans perte entre eux. De plus, les ports de connexion du système sont aisément configurables et le système peut ainsi être directement monté sur un circuit intégré. Un tel système peut avantageusement recevoir des composants électroniques de différentes natures et les relier entre eux de manière pratique. De plus, la surface arrière du composant électronique forme une partie de la surface du système électronique, ce qui améliore la dissipation de la chaleur. De préférence, le système comprend une pluralité de composants électroniques assemblés verticalement pour former un empilement. Ainsi, tous les connecteurs des composants électroniques sont connectés aux ports de connexion de manière optimale avec un encombrement réduit. Le composant électronique situé en bas de l'empilement permet d'évacuer la chaleur du système électronique de manière directe. Thanks to the invention, the electronic components can be conveniently and losslessly connected to each other. In addition, the connection ports of the system are easily configurable and the system can be directly mounted on an integrated circuit. Such a system can advantageously receive electronic components of different types and connect them conveniently. In addition, the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation. Preferably, the system comprises a plurality of vertically assembled electronic components to form a stack. Thus, all the connectors of the electronic components are connected to the connection ports optimally with a small footprint. The electronic component located at the bottom of the stack allows the heat to be evacuated directly from the electronic system.
De préférence encore, les composants électroniques possèdent la même orientation dans l'empilement. Selon un aspect de l'invention, le composant électronique comporte des plots conducteurs d'élévation rapportés sur les connecteurs dudit composant électronique. De tels plots d'élévation permettent de décaler verticalement les connecteurs par rapport à la surface avant du composant électronique. Autrement dit, les plots conducteurs s'étendent en saillie verticale de la surface avant du composant électronique. More preferably, the electronic components have the same orientation in the stack. According to one aspect of the invention, the electronic component comprises raised conductive pads on the connectors of said electronic component. Such elevation studs make it possible to vertically shift the connectors relative to the front surface of the electronic component. In other words, the conductive pads extend in vertical projection from the front surface of the electronic component.
De tels plots d'élévation permettent d'améliorer la compatibilité avec les interconnexions ou de décaler la position des connecteurs afin de limiter le risque d'interférence entre les interconnexions tridimensionnelles et le composant électronique. De manière préférée, les plots d'élévation rapportés sont formés préalablement à l'étape de réalisation d'interconnexion tridimensionnelle. De manière avantageuse, les plots d'élévation permettent de rendre compatible les interconnexions tridimensionnelles avec les connecteurs du composant électronique en formant une interface métallique compatible. Such elevation pads make it possible to improve the compatibility with the interconnections or to offset the position of the connectors in order to limit the risk of interference between the three-dimensional interconnections and the electronic component. Preferably, the reported elevation pads are formed prior to the step of making three-dimensional interconnection. Advantageously, the elevation pads make compatible the three-dimensional interconnections with the connectors of the electronic component by forming a compatible metal interface.
De manière préférée, le système électronique comporte : Preferably, the electronic system comprises:
- un premier empilement de composants électroniques formant un sous- système inférieur dont la surface arrière d'un composant électronique appartient à la surface avant du sous-système inférieure,  a first stack of electronic components forming a lower subsystem, the rear surface of an electronic component of which belongs to the front surface of the lower subsystem,
- un deuxième empilement de composants électroniques formant un sous- système supérieur et  a second stack of electronic components forming an upper subsystem and
- une couche de redistribution d'élévation formée entre le sous-système inférieur et le sous-système supérieur de manière à les connecter.  an elevation redistribution layer formed between the lower subsystem and the upper subsystem so as to connect them.
On forme de manière avantageuse un système électronique global formé d'une pluralité de sous-systèmes qui sont empilés verticalement ensemble. La couche de redistribution d'élévation permet de mettre en relation les ports de connexion du sous- système inférieur avec ceux du sous-système supérieur. An overall electronic system formed of a plurality of subsystems which are vertically stacked together is advantageously formed. The elevation redistribution layer makes it possible to connect the connection ports of the lower subsystem with those of the upper subsystem.
De préférence, le système électronique comporte une pluralité de sous-systèmes supérieurs, deux sous-systèmes supérieurs adjacents étant connectés par une couche de redistribution d'élévation. Ainsi, on peut former de manière itérative un grand nombre de sous-systèmes pour obtenir un système électronique global ayant de nombreuses fonctionnalités. Preferably, the electronic system comprises a plurality of upper subsystems, two adjacent upper subsystems being connected by an elevation redistribution layer. Thus, it is possible to iteratively form a large number of subsystems to achieve a global electronic system with many features.
L'invention concerne également un procédé de fabrication d'un système électronique comprenant : The invention also relates to a method for manufacturing an electronic system comprising:
- une étape d'application d'un élément sacrificiel sur une pièce de support,  a step of applying a sacrificial element to a support piece,
- une étape de dépôt d'au moins un composant électronique sur l'élément sacrificiel de manière adhésive, chaque composant électronique comportant une surface avant comportant une pluralité de connecteurs et une surface arrière opposée à la surface avant, la surface arrière du composant électronique étant positionnée sur l'élément sacrificiel,  a step of depositing at least one electronic component on the sacrificial element adhesively, each electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite the front surface, the rear surface of the electronic component being positioned on the sacrificial element,
- une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles réalisées par dépôt métallique de manière, d'une part, à combler des zones découvertes de l'élément sacrificiel pour former les ports de connexion du système et, d'autre part, à former une couche de redistribution reliant les connecteurs du composant électronique aux ports de connexion du système,  a step of producing a plurality of three-dimensional interconnections made by metal deposition so as, on the one hand, to fill open areas of the sacrificial element to form the connection ports of the system and, on the other hand, forming a redistribution layer connecting the connectors of the electronic component to the connection ports of the system,
- une étape d'encapsulation, et  an encapsulation step, and
une étape de séparation du système de l'élément sacrificiel. Grâce à l'invention, les composants électroniques peuvent être positionnés de manière précise sur l'élément sacrificiel, ce qui permet de former de manière optimale les interconnexions tridimensionnelles. De plus, comme l'élément sacrificiel peut être retiré, les ports de connexion du système sont rendus accessibles de manière pratique. Le système peut ainsi être directement monté sur un circuit intégré. Un tel système peut avantageusement recevoir des composants électroniques de différentes natures et les relier entre eux de manière pratique. De plus, la surface arrière du composant électronique forme une partie de la surface du système électronique, ce qui améliore la dissipation de la chaleur. De préférence, au moins un connecteur et au moins un port de connexion sont écartés d'une distance verticale supérieure à 10 μιτι, de préférence supérieure à 40 μιτι, et interconnectés tridimensionnellement. La direction verticale est définie orthogonalement à la direction horizontale selon laquelle s'étend l'élément sacrificiel. Un tel écartement impose des contraintes techniques importantes pour l'interconnexion. De manière préférée, au moins une interconnexion possède un rapport de forme supérieur à 2.5 :1 , de préférence supérieure à 5 :1 , de préférence encore supérieure à 10 :1 pour une distance verticale comprise entre 10 pm et 100 pm. Au-delà d'une distance verticale de Ι ΟΟμιτι, ce rapport de forme est supérieur à 1 .5 :1 , de préférence supérieur à 3 :1 , de préférence encore supérieur à 6 :1 . Pour rappel, le rapport de forme correspond à la distance verticale traversée par l'interconnexion sur sa largeur. a step of separating the system from the sacrificial element. Thanks to the invention, the electronic components can be positioned accurately on the sacrificial element, which optimally form three-dimensional interconnections. In addition, since the sacrificial element can be removed, the connection ports of the system are made conveniently accessible. The system can thus be directly mounted on an integrated circuit. Such a system can advantageously receive electronic components of different types and connect them conveniently. In addition, the back surface of the electronic component forms part of the surface of the electronic system, which improves heat dissipation. Preferably, at least one connector and at least one connection port are separated by a vertical distance greater than 10 μιτι, preferably greater than 40 μιτι, and three-dimensionally interconnected. The vertical direction is defined orthogonally to the horizontal direction along which the sacrificial element extends. Such spacing imposes significant technical constraints for the interconnection. Preferably, at least one interconnection has a shape ratio greater than 2.5: 1, preferably greater than 5: 1, more preferably greater than 10: 1 for a vertical distance of between 10 pm and 100 pm. Beyond a vertical distance of Ι ΟΟμιτι, this aspect ratio is greater than 1 .5: 1, preferably greater than 3: 1, more preferably greater than 6: 1. As a reminder, the aspect ratio corresponds to the vertical distance traversed by the interconnection over its width.
Un procédé soustractif tel qu'enseigné par US6774499B1 n'est pas adapté pour réaliser une interconnexion pour une distance verticale aussi importante et ayant un rapport de forme distance verticale sur largeur de l'interconnexion supérieur à 2 :1 . A subtractive method as taught by US6774499B1 is not suitable for providing interconnection for such a large vertical distance and having a vertical distance to interconnect width ratio of greater than 2: 1.
De préférence, le procédé comporte une pluralité d'étapes de report de composants électroniques et une pluralité d'étapes de réalisation de couches de redistribution tridimensionnelle. Cela permet avantageusement de former un empilement de composants électroniques connectés ensemble et aux ports de connexion internes de la couche de redistribution inférieure. Grâce à cette pluralité d'étapes, des composants électroniques de mêmes tailles ou de tailles différentes peuvent ainsi être intégrés dans un même système afin d'augmenter la densité de manière optimale. Preferably, the method comprises a plurality of electronic component transfer steps and a plurality of three-dimensional redistribution layer production steps. This advantageously makes it possible to form a stack of electronic components connected together and to the internal connection ports of the lower redistribution layer. Thanks to this plurality of steps, electronic components of the same size or different sizes can thus be integrated into the same system in order to increase the density optimally.
Selon un aspect préféré, le procédé comporte une étape de dépôt d'une couche de passivation de manière à couvrir la surface de l'élément sacrificiel et le composant électronique tout en maintenant découvert la pluralité de connecteurs du composant électronique et des zones de l'élément sacrificiel destinées à la formation des ports de connexion du système. According to a preferred aspect, the method comprises a step of depositing a passivation layer so as to cover the surface of the sacrificial element and the electronic component while maintaining the plurality of connectors of the electronic component and the zones of the sacrificial element for forming the connection ports of the system.
De manière préférée, l'élément sacrificiel se présente sous la forme d'un film adhésif, en particulier, à double face. Un tel élément sacrificiel est simple à manipuler pour un opérateur. En outre, un film adhésif double face permet de solidariser ensemble le support et les composants électroniques de manière temporaire lors de la réalisation du système. Preferably, the sacrificial element is in the form of an adhesive film, in particular, double-sided. Such a sacrificial element is simple to manipulate for an operator. In addition, a double-sided adhesive film secures the support and the electronic components together temporarily during the production of the system.
Selon un aspect de l'invention, l'élément sacrificiel se présente sous la forme d'une couche de résine adhésive. Selon un autre aspect de l'invention, l'élément sacrificiel se présente sous la forme d'une couche en polymère non adhésive. De préférence encore, l'élément sacrificiel est configuré pour perdre ses caractéristiques d'adhérence à partir d'une température prédéterminée. Un tel élément sacrificiel peut être retiré de manière pratique sans action mécanique pouvant endommager le système réalisé. De manière préférée, l'élément sacrificiel perd ses caractéristiques d'adhérence à partir d'une température inférieure à 250°C, ce qui évite un endommagement du système lors du chauffage. According to one aspect of the invention, the sacrificial element is in the form of an adhesive resin layer. According to another aspect of the invention, the sacrificial element is in the form of a non-adhesive polymer layer. More preferably, the sacrificial element is configured to lose its adhesion characteristics from a predetermined temperature. Such a sacrificial element can be conveniently removed without mechanical action that can damage the system being made. Preferably, the sacrificial element loses its adhesion characteristics from a temperature below 250 ° C, which avoids damage to the system during heating.
D'une autre manière préférée, l'élément sacrificiel est configuré pour perdre ses caractéristiques d'adhérence suite à une illumination, en particulier, par une source de lumière UV tel qu'un laser et/ou une lampe à mercure. Lors d'une telle illumination, l'élément sacrificiel convertit la lumière en énergie thermique ou génère un gaz, ce qui annule les caractéristiques d'adhérence. A cet effet, un élément sacrificiel du type « BrewerBond » ® de Brewer Science, « WSS » ® de 3M ou « SELFA » de Sekisui est particulièrement adapté. Selon un aspect préféré, l'élément sacrificiel est choisi parmi l'ensemble suivant : « ZoneBond » ®, « BrewerBond » ® et « WaferBond » ® de Brewer Science, « WSS » ® de 3M, « SELFA » ® de Sekisui et « Revalpha » ® de Nitto. De tels éléments sacrificiels présentent des caractéristiques optimales pour un coût réduit. Il va de soi que d'autres dénominations commerciales d'autres sociétés pourraient également convenir. In another preferred manner, the sacrificial element is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics. For this purpose, a BrewerBond® sacrificial element from Brewer Science, 3M WSS® or Sekisui's "SELFA" is particularly suitable. In a preferred aspect, the sacrificial element is selected from the following set of: "ZoneBond" ®, "BrewerBond" ® and "WaferBond" ® from Brewer Science, "WSS" ® from 3M, "SELFA" ® from Sekisui and " Revalpha® from Nitto. Such sacrificial elements have optimal characteristics for a reduced cost. It goes without saying that other trade names of other companies may also be appropriate.
De préférence encore, l'élément sacrificiel permet un décollage du système électronique par action mécanique sans détérioration. A cet effet, un élément sacrificiel du type « TM-X12 » ® de Hitachi Chemicals est particulièrement adapté. De préférence, le procédé comporte une étape de réalisation d'une ouverture dans le système de manière à découvrir la face avant d'au moins un composant électronique ayant une fonction de capteur. Ainsi, le procédé est compatible pour la réalisation d'un système ayant une fonction de capteur. De manière préférée, le procédé comprend au moins deux étapes de dépôt d'une couche de passivation afin de protéger les interconnexions dans le système. More preferably, the sacrificial element allows the electronic system to take off by mechanical action without deterioration. For this purpose, a sacrificial element of the type "TM-X12" ® of Hitachi Chemicals is particularly suitable. Preferably, the method comprises a step of making an opening in the system so as to discover the front face of at least one electronic component having a sensor function. Thus, the method is compatible for the realization of a system having a sensor function. Preferably, the method comprises at least two steps of depositing a passivation layer in order to protect the interconnections in the system.
De manière avantageuse, le procédé comprend au moins deux étapes de réalisation d'une pluralité d'interconnexions tridimensionnelles afin de former plusieurs couches de redistribution superposées. Des redistributions complexes peuvent alors être réalisées de manière pratique. Advantageously, the method comprises at least two steps of producing a plurality of three-dimensional interconnections in order to form a plurality of superimposed redistribution layers. Complex redistributions can then be carried out in a practical way.
De manière préférée, le procédé comprend une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles réalisées par dépôt métallique au-dessus d'un composant électronique afin de former une couche de redistribution supérieure reliée à des connecteurs dudit composant électronique. Ainsi, la surface supérieure et la surface inférieure du composant permettent une interconnexion du même type, ce qui facilite le montage du système dans un environnement dense. Preferably, the method comprises a step of producing a plurality of three-dimensional interconnections made by metal deposition on top of an electronic component to form an upper redistribution layer connected to connectors of said electronic component. Thus, the upper surface and the lower surface of the component allow interconnection of the same type, which facilitates the mounting of the system in a dense environment.
De préférence, le procédé comprend une étape de dépôt d'au moins un composant électronique sur la couche de redistribution supérieure, chaque composant électronique comportant une surface avant comportant une pluralité de connecteurs et une surface arrière opposée à la surface avant, la surface arrière du composant électronique étant positionnée en regard de la couche de redistribution supérieure. Des empilements de composants peuvent ainsi être montés en étage grâce à la présence de la couche de redistribution supérieure qui permet d'offrir des ports de connexion aisément accessible pour relier deux empilements différents. On peut ainsi former des systèmes très complexes. Preferably, the method comprises a step of deposition of at least one electronic component on the upper redistribution layer, each electronic component comprising a front surface having a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the electronic component being positioned opposite the upper redistribution layer. Stacks of components can thus be mounted in stages thanks to the presence of the upper redistribution layer which makes it possible to offer easily accessible connection ports for connecting two different stacks. Thus, very complex systems can be formed.
De préférence, le procédé comprend une étape de formation d'un composant passif tridimensionnel lors de l'étape de réalisation d'une pluralité d'interconnexions tridimensionnelles. Un tel composant passif tridimensionnel est réalisé de préférence en une seule étape, ce qui accélère la réalisation du système. Preferably, the method comprises a step of forming a three-dimensional passive component during the step of producing a plurality of three-dimensional interconnections. Such a three-dimensional passive component is preferably made in a single step, which accelerates the realization of the system.
Selon un aspect préféré, le procédé comprend une étape de dépôt d'une couche métallique sur la surface arrière d'au moins un composant électronique de manière à améliorer la dissipation thermique. De manière préférée, le procédé comporte une étape de dépôt d 'au moins deux composants électroniques superposés sur l 'élément sacrificiel et une étape de connexion des connecteurs desdits composants électroniques lors de l 'étape de réalisation d ' une pluralité d 'interconnexions tridimensionnelles. Des assemblages complexes peuvent avantageusement être réalisés dans un système. In a preferred aspect, the method comprises a step of depositing a metal layer on the rear surface of at least one electronic component so as to improve the heat dissipation. Preferably, the method comprises a step of depositing at least two electronic components superimposed on the sacrificial element and a step of connecting the connectors of said electronic components during the step of producing a plurality of three-dimensional interconnections. Complex assemblies can advantageously be made in a system.
Grâce à l 'invention, on réalise de manière pratique et peu onéreuse un système électronique comportant des composants électroniques hétérogènes en s'appuyant sur les interconnexions tridimensionnelles. On tire ainsi avantageusement partie de la dimension verticale pour augmenter la densité d 'intégration. De plus, une évacuation optimale de la chaleur est assurée via le contact direct entre la face arrière des composants actifs et le circuit imprimé (notamment une carte mère) sur lequel le système est soudé. PRESENTATION DES FIGURES Thanks to the invention, an electronic system comprising heterogeneous electronic components based on three-dimensional interconnections is produced in a practical and inexpensive manner. Advantage is thus advantageously taken of the vertical dimension to increase the integration density. In addition, optimal heat dissipation is provided via the direct contact between the rear face of the active components and the printed circuit (including a motherboard) on which the system is welded. PRESENTATION OF FIGURES
L'invention sera mieux comprise à la lecture de la description qui va suivre, donnée uniquement à titre d 'exemple, et se référant aux dessins annexés sur lesquels : The invention will be better understood on reading the description which follows, given solely by way of example, and referring to the appended drawings in which:
les figures 1 A-1 G sont des représentations schématiques d 'étapes de réalisation d ' un système selon l 'invention,  FIGS. 1A-1G are diagrammatic representations of steps for producing a system according to the invention,
la figure 2 est une représentation schématique d ' un composant électronique, la figure 3 est une représentation schématique d ' un système selon l 'invention solidarisé à un circuit intégré,  FIG. 2 is a schematic representation of an electronic component, FIG. 3 is a schematic representation of a system according to the invention integral with an integrated circuit,
les figures 4 et 5 représentent un système selon l 'invention en coupe (Figure 4) et selon une vue de dessous (Figure 5) avec une répartition des ports de connexion, la figure 6 est une représentation schématique d ' un système avec des billes de connexion rapportées,  Figures 4 and 5 show a system according to the invention in section (Figure 4) and in a view from below (Figure 5) with a distribution of the connection ports, Figure 6 is a schematic representation of a system with balls reported connections,
la figure 7 est une représentation schématique d ' un système avec une couche métallique de dissipation,  FIG. 7 is a schematic representation of a system with a dissipation metal layer,
- la figure 8 est une représentation schématique d ' un système avec deux couches de passivation,  FIG. 8 is a schematic representation of a system with two passivation layers,
la figure 9 est une représentation schématique d ' un système avec deux couches métalliques d 'interconnexions tridimensionnelles, la figure 10 est une représentation schématique d'un système avec une ouverture d'accès à un composant électronique ayant une fonction de capteur, les figures 1 1 et 12 représentent un système comportant un composant monté en surface, FIG. 9 is a schematic representation of a system with two metal layers of three-dimensional interconnections, FIG. 10 is a schematic representation of a system with an access opening to an electronic component having a sensor function, FIGS. 11 and 12 show a system comprising a surface-mounted component,
- la figure 13 représente un système comportant un composant passif tridimensionnel, et  FIG. 13 represents a system comprising a three-dimensional passive component, and
les figures 14, 15 et 16 représentent plusieurs formes de réalisation de systèmes comportant une couche de redistribution placée en partie supérieure de manière à se connecter à d'autres composants électroniques.  Figures 14, 15 and 16 show several embodiments of systems having a redistribution layer placed in the upper part so as to connect to other electronic components.
Les figures peuvent bien entendu servir à mieux définir l'invention le cas échéant. The figures can of course be used to better define the invention where appropriate.
DESCRIPTION D'UN OU PLUSIEURS MODES DE REALISATION ET DE MISE EN OEUVRE II va être présenté un système électronique comportant une pluralité de composants électroniques aptes à être montés sur un circuit imprimé afin de former une carte électronique. Une telle carte électronique peut être montée dans toute sorte d'appareils électroniques, par exemple, un ordinateur, une montre, un téléphone intelligent, un objet connecté, un vêtement, un équipement portable, etc. DESCRIPTION OF ONE OR MORE EMBODIMENTS AND IMPLEMENTATION There will be presented an electronic system comprising a plurality of electronic components adapted to be mounted on a printed circuit to form an electronic card. Such an electronic card can be mounted in all kinds of electronic devices, for example, a computer, a watch, a smart phone, a connected object, a garment, a portable equipment, etc.
On forme de manière avantageuse un système du type « System in package » qui comporte plusieurs composants électroniques. Dans l'exemple qui va suivre, il va être présenté la réalisation d'un système du type QFN ou LGA dont les ports de connexions s'étendent dans un même plan dans la continuité dudit système, c'est-à-dire, sans être en saillie. Advantageously, a "system in package" system is formed which comprises several electronic components. In the following example, it will be presented the realization of a system of the QFN or LGA type whose connection ports extend in the same plane in the continuity of said system, that is to say, without to be protruding.
Un exemple de fabrication d'un système selon l'invention va être présenté en référence à la figure 1 illustrant plusieurs étapes techniques de fabrication. Tout d'abord, en référence à la figure 1 A, il est représenté une étape d'application d'un élément sacrificiel 2 sur une pièce de support 1 . An example of manufacturing a system according to the invention will be presented with reference to Figure 1 illustrating several manufacturing technical steps. Firstly, with reference to FIG. 1A, there is shown a step of applying a sacrificial element 2 to a support piece 1.
De manière préférée, la pièce de support 1 se présente sous la forme d 'une surface plane à base de silicium, de verre, de céramique, de métal, de matériaux organiques ou tout type de matériau apte à servir de support. La pièce de support 1 est de préférence circulaire ou rectangulaire mais il va de soi que d'autres formes pourraient convenir. De préférence, la surface de support est supérieure à 2000 mm2. L'élément sacrificiel 2 possède une double fonction. Il permet, d'une part, de positionner de manière précise et robuste les composants électroniques 3 du système lors de sa réalisation et, d'autre part, de pouvoir les libérer lorsque le système est réalisé. Autrement dit, l'élément sacrificiel 2 forme un support temporaire pour les composants électroniques 3 afin que ceux-ci soient intégrés dans le système S. Preferably, the support part 1 is in the form of a flat surface based on silicon, glass, ceramic, metal, organic materials or any type of material suitable for use as a support. The support part 1 is preferably circular or rectangular, but it goes without saying that other shapes could be suitable. Preferably, the support surface is greater than 2000 mm 2. The sacrificial element 2 has a dual function. It makes it possible, on the one hand, to accurately and robustly position the electronic components 3 of the system during its production and, on the other hand, to be able to release them when the system is made. In other words, the sacrificial element 2 forms a temporary support for the electronic components 3 so that they are integrated in the system S.
De préférence encore, l'élément sacrificiel 2 se présente sous la forme d'une couche qui est organique, inorganique, polymérique ou métallique. L'élément sacrificiel 2 peut être déposé par enduction centrifuge, par pulvérisation (spray), par lamination, par pressage, par croissance ou analogue. A titre d'exemple, un élément sacrificiel 2 du type « ZoneBond » ®, « WaferBond » ® et « BrewerBond » ® de Brewer Science, « WSS » ® de 3M, « SELFA » ® de Sekisui et « Revalpha » ® de Nitto. De manière préférée, l'élément sacrificiel 2 se présente sous la forme d'un film adhésif qui est simple à manipuler, en particulier, à double face. De préférence, l'élément sacrificiel 2 est configuré pour perdre ses caractéristiques d'adhérence à partir d'une température prédéterminée. A cet effet, un élément sacrificiel 2 du type « Revalpha » ® de Nitto est particulièrement adapté. D'une autre manière préférée, l'élément sacrificiel 2 est configuré pour perdre ses caractéristiques d'adhérence suite à une illumination, en particulier, par une source de lumière UV tel qu'un laser et/ou une lampe à mercure. Lors d'une telle illumination, l'élément sacrificiel 2 convertit la lumière en énergie thermique ou génère un gaz, ce qui annule les caractéristiques d'adhérence. A cet effet, un élément sacrificiel 2 du type « BrewerBond » ® de Brewer Science ou « WSS » ® de 3M ou « SELFA » ® de Sekisui est particulièrement adapté. De préférence encore, l'élément sacrificiel 2 permet un décollage du système par action mécanique sans détérioration. A cet effet, un élément sacrificiel 2 du type « TM-X12 » ® de Hitachi Chemicals est particulièrement adapté. More preferably, the sacrificial element 2 is in the form of a layer which is organic, inorganic, polymeric or metallic. The sacrificial element 2 may be deposited by centrifugal coating, by spraying, by lamination, by pressing, by growth or the like. For example, a sacrificial element 2 of the "ZoneBond" ®, "WaferBond" ® and BrewerBond® ® by Brewer Science, "WSS" ® by 3M, "SELFA" by Sekisui and Revalpha by Nitto . In a preferred manner, the sacrificial element 2 is in the form of an adhesive film which is easy to handle, in particular double-sided. Preferably, the sacrificial element 2 is configured to lose its adhesion characteristics from a predetermined temperature. For this purpose, a sacrificial element 2 of the "Revalpha" ® type from Nitto is particularly suitable. In another preferred manner, the sacrificial element 2 is configured to lose its adhesion characteristics following illumination, in particular by a UV light source such as a laser and / or a mercury lamp. During such illumination, the sacrificial element 2 converts the light into thermal energy or generates a gas, which cancels the adhesion characteristics. For this purpose, a sacrificial element 2 of the "BrewerBond" ® type of Brewer Science or "WSS" ® of 3M or "SELFA" ® of Sekisui is particularly suitable. More preferably, the sacrificial element 2 allows takeoff of the system by mechanical action without deterioration. For this purpose, a sacrificial element 2 of the "TM-X12" type of Hitachi Chemicals is particularly suitable.
En référence à la figure 1 B, il est représenté une étape de dépôt de composants électroniques 3 sur l'élément sacrificiel 2 de manière adhésive. Comme illustré à la figure 2, chaque composant électronique 3 comporte une surface avant 3A comportant une pluralité de connecteurs 30 et une surface arrière 3B opposée à la surface avant 3A. De préférence, la surface arrière 3B de chaque composant électronique 3 est dépourvue de connecteurs 30. With reference to FIG. 1B, there is shown a step of depositing electronic components 3 on the sacrificial element 2 in an adhesive manner. As illustrated in Figure 2, each electronic component 3 has a front surface 3A having a plurality of connectors 30 and a rear surface 3B opposite to the front surface 3A. Of preferably, the rear surface 3B of each electronic component 3 is devoid of connectors 30.
Dans cet exemple, comme illustré à la figure 1 B, deux composants électroniques 3 sont positionnés directement en contact avec l'élément sacrificiel 2 et sont désignés composants électroniques de rang 1 . D'autres composants électroniques peuvent être positionnés en superposition sur les composants électroniques 3 de rang 1 , ces composants électroniques 3 étant désignés composants électroniques de rang 2. Lorsqu'un composant électronique 3 est superposé sur un composant électronique de rang donné n, le composant électronique 3 superposé possède un rang n+1 . En référence à la partie droite de la figure 1 B, un composant électronique de rang 2 est positionné sur un des composants électroniques de rang 1 . La surface arrière 3B des composant électroniques 3 de rang 1 est positionnée sur l'élément sacrificiel 2 de manière à s'étendre au niveau de la surface avant du système électronique S pour évacuer la chaleur de manière optimale. In this example, as illustrated in FIG. 1B, two electronic components 3 are positioned directly in contact with the sacrificial element 2 and are designated electronic components of rank 1. Other electronic components can be positioned in superposition on the electronic components 3 of rank 1, these electronic components 3 being designated electronic components of rank 2. When an electronic component 3 is superimposed on an electronic component of given rank n, the component 3 superimposed electronic has a rank n + 1. With reference to the right-hand part of FIG. 1B, an electronic component of rank 2 is positioned on one of the electronic components of rank 1. The rear surface 3B of the electronic components 3 of rank 1 is positioned on the sacrificial element 2 so as to extend at the front surface of the electronic system S to remove the heat optimally.
Le positionnement des composants électroniques 3 est réalisé de préférence par une méthode de report dite de « pick and place ». Lorsque l'élément sacrificiel 2 est adhésif, les composants électroniques 3 de rang 1 sont stables sur l'élément sacrificiel 2. Lorsque l'élément sacrificiel 2 n'est pas adhésif, il peut être ajouté une couche adhésive entre les composants électroniques 3 et l'élément sacrificiel 2. The positioning of the electronic components 3 is preferably performed by a so-called "pick and place" transfer method. When the sacrificial element 2 is adhesive, the electronic components 3 of rank 1 are stable on the sacrificial element 2. When the sacrificial element 2 is not adhesive, an adhesive layer can be added between the electronic components 3 and the sacrificial element 2.
Par ailleurs, une couche de colle est appliquée entre deux composants électroniques 3 superposés. La couche de colle est déposée entre la surface arrière 3B du composant électronique 3 de rang supérieur et la surface avant 3A du composant électronique 3 de rang inférieur. Le positionnement précis permet de garantir une interconnexion optimale. Furthermore, a layer of adhesive is applied between two superimposed electronic components 3. The adhesive layer is deposited between the rear surface 3B of the electronic component 3 of higher rank and the front surface 3A of the electronic component 3 of lower rank. Precise positioning ensures optimum interconnection.
De manière préférée, l'épaisseur verticale totale (composant(s) électronique(s) 3 et couche(s) de colle) est supérieure à 1 Ομιτι, plus particulièrement, supérieure à 40μιτι. Les flancs des composants électroniques 3 peuvent être droits, en dépouille et/ou en contre dépouille. Par souci de clarté, seuls des composants électroniques 3 ayant des flancs droits ont été utilisés sur les figures. En référence à la figure 1 C, il est représenté une étape de dépôt d'une couche de passivation 4 de manière à couvrir la surface de l'élément sacrificiel 2 et la surface avant 3A du composant électronique 3 tout en formant des ouvertures 40 maintenant découvert la pluralité de connecteurs 30 du composant électronique 3 et des zones de l'élément sacrificiel 2 de manière à former des ports de connexion. Preferably, the total vertical thickness (electronic component (s) 3 and glue layer (s)) is greater than 1 Ομιτι, more particularly greater than 40μιτι. The flanks of the electronic components 3 can be straight, undercut and / or undercut. For the sake of clarity, only electronic components 3 having straight flanks have been used in the figures. With reference to FIG. 1C, there is shown a step of depositing a passivation layer 4 so as to cover the surface of the sacrificial element 2 and the front surface 3A of the electronic component 3 while forming openings 40 now discovered the plurality of connectors 30 of the electronic component 3 and the areas of the sacrificial element 2 so as to form connection ports.
Selon le besoin du système, la couche de passivation 4 est déposée d'une manière conforme ou d'une manière à adapter l'angle des flancs des composants électroniques 3. La couche de passivation 4 peut être composée d'un matériau organique ou inorganique, tel qu'un oxyde de semi-conducteur, un oxyde de métal, un polymère ou tout autre matériau électriquement isolant. Elle peut être déposée par enduction centrifuge, par spray, par lamination, par pressage, par croissance, par impression (inkjet), par dépôt sous vide ou par tout type de dépôt connu par l'homme du métier. Toujours en référence à la figure 1 C, des ouvertures 40 sont réalisées dans la couche de passivation 4, afin de découvrir les connecteurs 30 des composants électroniques 3 et des zones de l'élément sacrificiel 2. De préférence, les ouvertures 40 sont réalisées à l'aide d'un procédé de photolithographie ou à l'aide d'une gravure par voie chimique humide et/ou sèche, par plasma ou par laser. De manière préférée, des matériaux photosensibles sont privilégiés compte tenu des avantages offerts par les procédés de photolithographie. According to the need of the system, the passivation layer 4 is deposited in a manner conforming or in a manner to adapt the angle of the flanks of the electronic components 3. The passivation layer 4 can be composed of an organic or inorganic material , such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It may be deposited by centrifugal coating, by spray, by lamination, by pressing, by growth, by printing (inkjet), by vacuum deposition or by any type of deposit known to those skilled in the art. Still with reference to FIG. 1C, openings 40 are made in the passivation layer 4, in order to discover the connectors 30 of the electronic components 3 and the zones of the sacrificial element 2. Preferably, the openings 40 are made to using a photolithography process or using wet and / or dry chemical etching, plasma or laser etching. In a preferred manner, photosensitive materials are preferred in view of the advantages offered by the photolithography processes.
Dans le cas où les surfaces et les flancs des composants électroniques 3 sont isolants sauf au niveau des connecteurs 30, le dépôt de la couche de passivation 4 peut ne pas être appliqué, réduisant ainsi le temps et le coût de fabrication. In the case where the surfaces and sides of the electronic components 3 are insulating except at the connectors 30, the deposition of the passivation layer 4 may not be applied, thus reducing the time and cost of manufacture.
En référence à la partie droite de la figure 1 C, le système électronique S comporte plusieurs composants électroniques 3 assemblés verticalement pour former un empilement. Les composants électroniques 3 possèdent la même orientation dans l'empilement. La surface arrière 3B du composant électronique 3 de rang supérieur est montée sur la surface avant 3A du composant électronique 3 de rang inférieur. Il va de soi que le système électronique S pourrait comprendre un empilement d'un grand nombre de composants électroniques 3 de natures différentes. De manière préférée, chaque composant électronique 3 de rang supérieur d'un empilement possède des dimensions inférieures au composant électronique 3 de rang inférieur de manière à former un empilement facilitant la formation d'interconnexions tridimensionnelles 5 entre les différentes composants électroniques 3. La compacité et la densité d'intégration est ainsi augmentée de manière pratique. With reference to the right part of FIG. 1C, the electronic system S comprises several electronic components 3 assembled vertically to form a stack. The electronic components 3 have the same orientation in the stack. The rear surface 3B of the electronic component 3 of higher rank is mounted on the front surface 3A of the electronic component 3 of lower rank. It goes without saying that the electronic system S could comprise a stack of a large number of electronic components 3 of different natures. Preferably, each electronic component 3 of higher rank of a stack has dimensions smaller than the electronic component 3 of lower rank so as to form a stack facilitating the formation of three-dimensional interconnections 5 between the various electronic components 3. The compactness and the integration density is thus increased in a practical way.
De manière préférée, l'empilement est pyramidal ou en marche d'escaliers. Selon ce dernier cas, il est possible d'empiler des composants électroniques 3 ayant une taille identique ou bien des composants électroniques 3 de taille plus grande par-dessus de composants électroniques 3 de taille plus petite. Il va de soi que les composants électroniques 3 peuvent avoir des dimensions différentes. Preferably, the stack is pyramidal or walking stairs. According to the latter case, it is possible to stack electronic components 3 having an identical size or electronic components 3 of larger size over smaller electronic components 3. It goes without saying that the electronic components 3 may have different dimensions.
En référence à la figure 1 D, il est représenté une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles 5 réalisées par dépôt métallique de manière à relier les zones découvertes 40 de l'élément sacrificiel 2 aux connecteurs 30 du composant électronique 3, les zones comblées de l'élément sacrificiel 2 formant des ports de connexion 50. With reference to FIG. 1D, there is shown a step of producing a plurality of three-dimensional interconnections 5 made by metal deposition so as to connect the exposed zones 40 of the sacrificial element 2 to the connectors 30 of the electronic component 3, the filled areas of the sacrificial element 2 forming connection ports 50.
Les interconnexions tridimensionnelles 5 ainsi que des ports de connexion 50 sont formés pour interconnecter les connecteurs 30 des composants électroniques 3. Les interconnexions tridimensionnelles 5 sont connues en soi, en particulier, par la demande de brevet FR2965659. Dans cet exemple, pour réaliser les interconnexions tridimensionnelles 5 et les ports de connexion 50, le procédé comporte : The three-dimensional interconnections 5 and connection ports 50 are formed to interconnect the connectors 30 of the electronic components 3. The three-dimensional interconnections 5 are known per se, in particular by the patent application FR2965659. In this example, to achieve the three-dimensional interconnections 5 and the connection ports 50, the method comprises:
une étape de dépôt d'une couche métallique par évaporation, par pulvérisation ou autre, qui remplit à la fois une fonction de base d'accrochage et de croissance du métal constituant les interconnexions tridimensionnelles 5 et les ports de connexion 50. Cette couche métallique peut être composée d'un unique ou de plusieurs matériaux conducteurs de l'électricité et/ou semi-conducteurs. - une étape de dépôt d'une couche épaisse de résine photosensible et une étape de réalisations d'ouvertures par des techniques de photolithographie, par ablation laser ou autres, afin de créer un moule nécessaire au dépôt du métal constituant les interconnexions tridimensionnelles 5. Ces ouvertures définissent la forme des interconnexions tridimensionnelles 5 ainsi que celles des pistes métalliques formant la couche de redistribution tridimensionnelle (présentée par la suite) et les ports de connexion 50. Selon le besoin d'intégration, l'épaisseur de la couche de résine photosensible peut varier de 20 à 700μιτι et le rapport de forme (résolution) de 0.5 :1 à 50 :1 . a step of depositing a metal layer by evaporation, by sputtering or the like, which fulfills both a basic function of attachment and growth of the metal constituting the three-dimensional interconnections 5 and the connection ports 50. This metal layer can be composed of one or more electrically conductive materials and / or semiconductors. a step of depositing a thick layer of photosensitive resin and a step of making apertures by photolithography, laser ablation or other techniques in order to create a mold necessary for depositing the metal constituting the three-dimensional interconnections. openings define the shape of the three-dimensional interconnections as well as those of the metal tracks forming the three-dimensional redistribution layer (presented by following) and the connection ports 50. Depending on the need for integration, the thickness of the photoresist layer may vary from 20 to 700 μm and the aspect ratio (resolution) from 0.5: 1 to 50: 1.
une étape de dépôt d'une couche de métal par électrolyse ou toute autre technique de croissance de métal. Le métal déposé peut être du cuivre, de l'or, de l'argent, du nickel, un alliage de métaux ou tout autre matériau conducteur de l'électricité.  a step of depositing a metal layer by electrolysis or any other metal growth technique. The deposited metal may be copper, gold, silver, nickel, a metal alloy, or any other electrically conductive material.
une étape de dissolution du moule de résine et une étape de gravure de la couche d'accrochage. Ces procédés sont connus par l'homme du métier. Cependant, dans le cas où la coche d'accrochage contient de l'or, une solution à base de KI+12 et d'additifs pourrait être utilisée pour graver cette couche sans abîmer les interconnexions tridimensionnelles 5.  a step of dissolving the resin mold and a step of etching the bonding layer. These methods are known to those skilled in the art. However, in the case where the attachment check mark contains gold, a solution based on KI + 12 and additives could be used to etch this layer without damaging the three-dimensional interconnections 5.
Dans cet exemple, les ports de connexion 50 du système S et les connecteurs 30 des composants électroniques 3 sont respectivement reliés entre eux par la couche de redistribution formée par les interconnexions tridimensionnelles 5 réalisées par dépôt métallique. Les ports de connexion 50 sont formés simultanément avec lesdites interconnexions tridimensionnelles 5. De manière avantageuse, même en cas de pluralité de composants électroniques 3, les interconnexions tridimensionnelles 5 sont réalisées au cours d'une seule et même étape, ce qui procure un gain de temps important. Le nombre de connecteurs 30 reliés entre eux dépend du degré d'interaction entre les deux composants électroniques 3 dans le système électronique S. La couche de redistribution planaire permet d'améliorer le routage entre les composants électroniques 3, en particulier, en cas de forte densité de connecteurs 30. In this example, the connection ports 50 of the system S and the connectors 30 of the electronic components 3 are respectively interconnected by the redistribution layer formed by the three-dimensional interconnections 5 made by metal deposition. The connection ports 50 are formed simultaneously with said three-dimensional interconnections 5. Advantageously, even in the case of a plurality of electronic components 3, the three-dimensional interconnections 5 are made in one and the same step, which provides a gain of important time. The number of connectors 30 connected to each other depends on the degree of interaction between the two electronic components 3 in the electronic system S. The planar redistribution layer makes it possible to improve the routing between the electronic components 3, in particular in case of strong density of connectors 30.
En référence à la figure 1 E, il est représenté une étape d'encapsulation 6 de manière à encapsuler les composants électroniques 3 et les interconnexions 5. De manière préférée, la couche d'encapsulation 6 est réalisée en polymère, par exemple en époxy, et chargé ou non de particules telles que de la silice, de l'alumine, etc. mais il va de soi que d'autres matériaux analogues pourraient convenir. De manière préférée, l'étape d'encapsulation est réalisée par sérigraphie, moulage par injection, par transfert ou par pression. Une telle couche d'encapsulation 6 permet avantageusement d'améliorer la robustesse mécanique ainsi que la fiabilité du système électronique S. En référence à la figure 1 F, il est représenté une étape de séparation des systèmes S de l'élément sacrificiel 2. L'étape de séparation dépend de la nature de l'élément sacrificiel 2. A cet effet, l'étape de séparation peut être réalisée par dissolution ou gravure, par glissement ou en désactivant l'élément sacrificiel 2 à l'aide d'un laser, d'UV ou en le chauffant comme dans le cas du « Revalpha » ® de Nitto. Dans cet exemple, l'ensemble est chauffé à une température comprise entre 120°C et 250°C en fonction de l'élément sacrificiel 2 utilisé, ce qui n'endommage pas le système S. En référence à la figure 1 G, il est représenté une étape de découpe de manière à séparer les systèmes électroniques S afin de pouvoir les utiliser de manière individuelle. On obtient avantageusement un système S se présentant sous la forme d'un boîtier du type QFN comportant des ports de connexion 50 plats. With reference to FIG. 1E, an encapsulation step 6 is represented so as to encapsulate the electronic components 3 and the interconnects 5. Preferably, the encapsulation layer 6 is made of polymer, for example epoxy, and loaded or not with particles such as silica, alumina, etc. but it goes without saying that other similar materials might be suitable. Preferably, the encapsulation step is performed by screen printing, injection molding, transfer or by pressure. Such an encapsulation layer 6 advantageously makes it possible to improve the mechanical robustness as well as the reliability of the electronic system S. With reference to FIG. 1F, there is shown a step of separating the systems S from the sacrificial element 2. The separation step depends on the nature of the sacrificial element 2. For this purpose, the separation step can be performed by dissolution or etching, by sliding or by deactivating the sacrificial element 2 by means of a laser, UV or by heating it as in the case of "Revalpha" ® by Nitto. In this example, the assembly is heated to a temperature between 120 ° C and 250 ° C depending on the sacrificial element 2 used, which does not damage the system S. Referring to Figure 1 G, it is shown a cutting step so as to separate the electronic systems S so that they can be used individually. Advantageously, a system S is in the form of a QFN-type box having flat connection ports 50.
En référence à la figure 3, on obtient ainsi un système électronique S qui peut être solidarisé à un circuit imprimé 9 par différentes techniques, en particulier, par soudure des ports de connexion 50 du système électronique S aux ports de connexion 90 du circuit imprimé 9. La solidarisation peut être réalisée avec de l'étain, des alliages ou des colles conductrices ou isolantes. With reference to FIG. 3, an electronic system S is thus obtained that can be secured to a printed circuit board 9 by various techniques, in particular by soldering the connection ports 50 of the electronic system S to the connection ports 90 of the printed circuit board 9. Bonding can be carried out with tin, alloys or conductive or insulating glues.
En référence aux figures 4 et 5, lorsque les applications nécessitent un nombre important d'entrées-sorties, le système S peut intégrer plusieurs ports de connexion 50 arrangés sur sa périphérie. Les interconnexions permettent de former une couche de redistribution optimale, d'une part, entre les connecteurs 30 et, d'autre part, entre les connecteurs 30 et les ports de connexion 50. De manière avantageuse, il est à noter que le nombre de rangées de ports de connexion 50 n'est pas limité par comparaison à un boîtier QFN classique. With reference to FIGS. 4 and 5, when the applications require a large number of inputs / outputs, the system S can integrate a plurality of connection ports 50 arranged on its periphery. The interconnections make it possible to form an optimal redistribution layer, on the one hand, between the connectors 30 and, on the other hand, between the connectors 30 and the connection ports 50. Advantageously, it should be noted that the number of Rows of connection ports 50 is not limited by comparison to a conventional QFN package.
Plusieurs autres formes de réalisation d'un système électronique S selon l'invention sont représentées en référence aux figures 6 à 14. Par souci de clarté et de concision, les éléments identiques ou analogues entre les autres formes de réalisation sont référencés avec la même référence numérique, seules les différences entre les formes de réalisation sont présentées en détails. En référence à la figure 6, afin de permettre une solidarisation par retournement, le système S peut comprendre des billes conductrices 150 solidarisées aux ports de connexion 50 du système S pour se connecter à un circuit imprimé 9. De telles billes conductrices 150 sont connues de l'homme du métier sous leur désignation anglaise « micro-bump » et ne seront pas présentées en détails. Several other embodiments of an electronic system S according to the invention are shown with reference to FIGS. 6 to 14. For the sake of clarity and brevity, identical or similar elements between the other embodiments are referenced with the same reference. numerical, only the differences between the embodiments are presented in detail. With reference to FIG. 6, in order to allow a joining by reversal, the system S may comprise conductive balls 150 secured to the connection ports 50 of the system S to connect to a printed circuit 9. Such conductive balls 150 are known to the person skilled in the art under their English designation "micro-bump" and will not be presented in detail.
En référence à la figure 7, afin d'améliorer la dissipation thermique, une couche métallique 91 peut être appliquée sur la surface arrière 3B des composants électroniques 3. Cette couche métallique 91 peut être appliquée avant le report des composants électroniques 3 sur l'élément sacrificiel 2 ou après l'étape d'encapsulation. With reference to FIG. 7, in order to improve the heat dissipation, a metal layer 91 may be applied to the rear surface 3B of the electronic components 3. This metal layer 91 may be applied before the transfer of the electronic components 3 to the element sacrificial 2 or after the encapsulation step.
En référence à la figure 8, en fonction des besoins, une deuxième couche de passivation 4' peut être appliquée après la réalisation des interconnexions 5 et avant l'étape d'encapsulation. En référence à la figure 9, en fonction de la complexité, les étapes de dépôt des couches de passivation 4, 4' et de dépôt des interconnexions tridimensionnelles 5, 5' peuvent être répétées pour répondre au besoin d'intégration de systèmes S à haute densité. Autrement dit, on forme des couches de redistribution superposées pour permettre des liaisons complexes entre un grand nombre de connecteurs 30 et un grand nombre de ports de connexion 50. Cela est particulièrement avantageux pour router un nombre très grand d'entrées/sorties, pour intégrer séparément les niveaux d'alimentations ou pour intégrer un bouclier protégeant le circuit des interférences électromagnétiques et électrostatiques, etc. En répétant les étapes de passivation et de réalisation d'interconnexions 5, il devient possible de réaliser un système S comportant plusieurs couches de métal ou un système comportant des composants électroniques 3 de même taille qui sont empilés verticalement. With reference to FIG. 8, as needed, a second passivation layer 4 'may be applied after the completion of the interconnections 5 and before the encapsulation step. With reference to FIG. 9, depending on the complexity, the deposition steps of the passivation layers 4, 4 'and deposition of the three-dimensional interconnections 5, 5' can be repeated to meet the need for integration of high-level S systems. density. In other words, superimposed redistribution layers are formed to allow complex links between a large number of connectors 30 and a large number of connection ports 50. This is particularly advantageous for routing a very large number of inputs / outputs, to integrate separately power supply levels or to incorporate a shield protecting the circuit from electromagnetic and electrostatic interference, etc. By repeating the passivation and interconnection steps 5, it becomes possible to produce a system S comprising several metal layers or a system comprising electronic components 3 of the same size which are stacked vertically.
En référence à la figure 10, lorsqu'un des composants électroniques 3 possède une fonction de capteur, une ouverture 60 est réalisée dans le système S afin que la face avant 3A du composant électronique 3, ayant une fonction de capteur, soit découverte. Cette ouverture 60 peut être créée pendant l'étape d'encapsulation, en particulier par « transfer molding » ou après encapsulation en gravant localement la couche d'encapsulation ou à l'aide d'autres techniques connues de l'homme du métier. En référence aux figures 1 1 à 12, le système électronique S comporte un organe électronique additionnel XI , par exemple un composant du type « Composé Monté en Surface », qui peut être positionné dans le système S après la réalisation des interconnexions tridimensionnelles 5 (Figure 1 1 ) ou avant la réalisation des interconnexions tridimensionnelles 5 (Figure 12). L'organe électronique additionnel XI est ainsi disposé à côté de l'empilement des composants électroniques 3. Les pertes sont alors réduites. Lorsque l'organe électronique additionnel XI est solidarisé avant la réalisation des interconnexions tridimensionnelles 5, ce sont les interconnexions tridimensionnelles 5 qui permettent de réaliser la connexion, ce qui limite le nombre d'étapes de fabrication du système S. With reference to FIG. 10, when one of the electronic components 3 has a sensor function, an opening 60 is made in the system S so that the front face 3A of the electronic component 3, having a sensor function, is uncovered. This opening 60 may be created during the encapsulation step, in particular by "transfer molding" or after encapsulation by locally etching the encapsulation layer or using other techniques known to those skilled in the art. With reference to FIGS. 1 to 12, the electronic system S comprises an additional electronic element XI, for example a component of the "Surface-Mounted Compound" type, which can be positioned in the system S after the realization of the three-dimensional interconnections 5 (FIG. 1 1) or before the realization of the three-dimensional interconnections 5 (Figure 12). The additional electronic element XI is thus disposed next to the stack of the electronic components 3. The losses are then reduced. When the additional electronic element XI is secured before the realization of the three-dimensional interconnections 5, it is the three-dimensional interconnections 5 that make the connection possible, which limits the number of manufacturing steps of the system S.
En référence à la figure 13, en lieu et place d'un organe électronique additionnel XI monté à côté du ou des composants électroniques 3, le système électronique S comporte un ou plusieurs composants passifs tridimensionnels X2 qui sont, de préférence, réalisés simultanément aux interconnexions tridimensionnelles 5. Les pertes sont alors réduites et la fabrication rapide et aisée. With reference to FIG. 13, in place of an additional electronic element XI mounted next to the electronic component or components 3, the electronic system S comprises one or more three-dimensional passive components X2 which are preferably produced simultaneously with the interconnections three-dimensional 5. The losses are then reduced and the manufacture quick and easy.
Selon un aspect de l'invention non représenté, le composant électronique comporte des plots conducteurs d'élévation rapportés sur les connecteurs 30 dudit composant électronique 3. De tels plots d'élévation permettent de décaler verticalement les connecteurs 30 par rapport à la surface avant 3A du composant électronique 3. Autrement dit, les plots conducteurs s'étendent en saillie verticale de la surface avant 3A du composant électronique 3. De tels plots d'élévation permettent d'améliorer la compatibilité avec les interconnexions 5 ou de décaler la position des connecteurs 30 afin de limiter le risque d'interférence entre les interconnexions tridimensionnelles 5 et le composant électronique 3. De manière préférée, les plots d'élévation rapportés sont formés préalablement à l'étape de réalisation d'interconnexion tridimensionnelle. De manière avantageuse, les plots d'élévation permettent de rendre compatible les interconnexions tridimensionnelles 5 avec les connecteurs 30 du composant électronique 3 en formant une interface métallique compatible. According to one aspect of the invention not shown, the electronic component comprises raised conductive pads reported on the connectors 30 of said electronic component 3. Such elevation pads are used to vertically shift the connectors 30 relative to the front surface 3A of the electronic component 3. In other words, the conductive pads extend in vertical projection from the front surface 3A of the electronic component 3. Such elevation pads make it possible to improve the compatibility with the interconnections 5 or to offset the position of the connectors In order to limit the risk of interference between the three-dimensional interconnections 5 and the electronic component 3. Preferably, the reported elevation pads are formed prior to the three-dimensional interconnection realization step. Advantageously, the elevation pads make it possible to make the three-dimensional interconnections 5 compatible with the connectors 30 of the electronic component 3 by forming a compatible metal interface.
En référence aux figures 14 à 15, il est représenté plusieurs formes de réalisation de systèmes S comportant une couche de redistribution supérieure 5" créée sur un ou plusieurs composants électroniques 3 du système S de manière à permettre le montage de composants électroniques additionnels sur la face supérieure du système S. De manière préférée, en référence aux figures 14 et 15, la couche de redistribution supérieure 5" est planaire est réalisée au cours de la même étape de réalisation que la pluralité d'interconnexions tridimensionnelles 5 telle que présentée précédemment. With reference to FIGS. 14 to 15, there are shown several embodiments of systems S comprising an upper redistribution layer 5 "created on one or more electronic components 3 of the system S so as to allow the assembly additional electronic components on the upper face of the system S. Preferably, with reference to FIGS. 14 and 15, the upper redistribution layer 5 "is planar is made during the same step of realization as the plurality of three-dimensional interconnections 5 as previously presented.
En référence à la figure 14, le système S comporte une couche de redistribution supérieure 5" créée au-dessus des composants électroniques 3 pour permettre le positionnement de billes conductrices 150". De telles billes conductrices 150" permettent une connexion à d'autres composants électroniques ou à un circuit intégré. Grâce à la couche de redistribution supérieure 5", les billes conductrices 150" peuvent être placées aux endroits désirés sur la surface supérieure du système S. With reference to FIG. 14, the system S comprises an upper redistribution layer 5 "created above the electronic components 3 to allow the positioning of conductive balls 150". Such conductive balls 150 "allow connection to other electronic components or to an integrated circuit.Through the upper redistribution layer 5", the conductive balls 150 "can be placed at the desired locations on the upper surface of the system S.
En référence à la figure 15, le système S comporte une couche de redistribution supérieure 5" créée au-dessus des composants électroniques 3 sur laquelle sont montés un premier composant électronique X3 par l'intermédiaire de billes conductrices 150" et un deuxième composant électronique X4 par l'intermédiaire de fils micro soudés. Ainsi, une intégration verticale mixte peut être réalisée, ce qui offre une grande flexibilité de conception. Il va de soi que les composants électroniques additionnels peuvent être protégés par une couche d'encapsulation, ce qui offre une protection mécanique et chimique desdits composants additionnels. Cette encapsulation peut être réalisée en même temps que le dépôt de la couche d'encapsulation 6 du système S ou de manière séparée après encapsulation dudit système S. With reference to FIG. 15, the system S comprises an upper redistribution layer 5 "created above the electronic components 3 on which a first electronic component X3 is mounted via conductive balls 150" and a second electronic component X4. via micro-welded wires. Thus, a mixed vertical integration can be achieved, which offers great design flexibility. It goes without saying that the additional electronic components can be protected by an encapsulation layer, which provides mechanical and chemical protection of said additional components. This encapsulation can be performed simultaneously with the deposition of the encapsulation layer 6 of the system S or separately after encapsulation of said system S.
En référence à la figure 16, il peut être réalisé un système S comportant une pluralité de sous-systèmes SSl , SS2 séparés par une ou une plusieurs couches de redistribution d'élévation 5" '. De manière analogue aux figures 14 et 15, la couche de redistribution d'élévation 5" ' est créée entre un sous-système inférieur SSl comprenant un ou plusieurs composants électroniques 3 et un sous-système supérieure SS2 comprenant un ou plusieurs composants électroniques 3. De manière avantageuse, la couche de redistribution d'élévation 5" ' permet de former un système électronique S comportant un empilement de sous-systèmes SSl , SS2 comportant chacun un empilement de composants électroniques 3 tel que présenté précédemment. De manière avantageuse, la couche de redistribution d'élévation 5" ' remplit la fonction de l'élément sacrificiel 2 lorsque l'on souhaite former un sous-système supérieur SS2 sur un sous-système inférieur SSl . Autrement dit, on forme le sous-système inférieur SSl comme enseigné précédemment en référence à la figure 1 puis on forme la couche de redistribution d'élévation 5" ' et on forme le sous-système supérieur SS2 en utilisant la couche de redistribution d'élévation 5" ' en lieu et place de l'élément sacrificiel 2. On forme ainsi un système électronique S en élévation appelé « Build-up ». La couche de redistribution d'élévation 5" ' peut être réalisée en une ou plusieurs étapes. Dans cet exemple, elle est réalisée en une première étape de réalisation d'interconnexion tridimensionnelles et une deuxième étape de réalisation d'une couche de redistribution planaire. De préférence, la couche de redistribution d'élévation 5" ' est plus grande que la surface du composant électronique 3 le plus haut de du sous-système inférieur SSl de manière à coopérer de manière optimale avec le composant électronique le plus bas du sous-système supérieur SS2. La couche de redistribution d'élévation 5" ' permet avantageusement de former la liaison entre les strates. De manière préférée et selon le besoin du système, une couche de passivation est déposée en dessous et/ou au-dessus de la couche de redistribution d'élévation 5" '. Des ouvertures sont réalisées dans cette couche pour assurer les liaisons électriques entre les interconnexions tridimensionnelles 5 et la couche de redistribution d'élévation 5" '. With reference to FIG. 16, a system S may be made comprising a plurality of subsystems SS1, SS2 separated by one or more elevation redistribution layers 5 ". In a similar manner to FIGS. Elevation redistribution layer 5 "'is created between a lower subsystem SS1 comprising one or more electronic components 3 and an upper subsystem SS2 comprising one or more electronic components 3. Advantageously, the redistribution layer of elevation 5 "'makes it possible to form an electronic system S comprising a stack of subsystems SS1, SS2, each comprising a stack of electronic components 3 as presented above, advantageously the elevation redistribution layer 5''fulfills the function of the sacrificial element 2 when it is desired to form an upper subsystem SS2 on a lower subsystem SSl. In other words, the lower subsystem SS1 is formed as previously taught with reference to FIG. 1, then the elevation redistribution layer 5 "'is formed and the upper subsystem SS2 is formed using the redistribution layer of FIG. elevation 5 "'in place of the sacrificial element 2. An electronic system S in elevation called" Build-up "is thus formed. The elevation redistribution layer 5 "'can be carried out in one or more steps, in this example it is carried out in a first step of three-dimensional interconnection realization and a second step of realization of a planar redistribution layer. Preferably, the elevation redistribution layer 5 "'is larger than the surface of the highest electronic component 3 of the lower subsystem SS1 so as to cooperate optimally with the lowest electronic component of the sub-system. superior system SS2. The elevation redistribution layer 5 "advantageously makes it possible to form the bond between the layers Preferably, and according to the need of the system, a passivation layer is deposited below and / or above the redistribution layer. elevation 5 "'. Openings are made in this layer to provide the electrical connections between the three-dimensional interconnects 5 and the elevation redistribution layer 5 "'.
Grâce à l'invention, on peut réaliser des systèmes électroniques S permettant une intégration hétérogène et tridimensionnelle. Ce type d'intégration permet une forte miniaturisation ainsi qu'une amélioration des performances des systèmes S sans utiliser des technologies complexes telles que celle des vias traversants. Thanks to the invention, one can realize electronic systems S for heterogeneous integration and three-dimensional. This type of integration allows a strong miniaturization as well as an improvement of the performances of the systems S without using complex technologies such as through vias.
De manière avantageuse, la méthode de fabrication ne nécessite qu'un faible nombre d'étapes technologiques permettant de réaliser plusieurs systèmes électroniques S simultanément, ce qui réduit le temps et le coût de fabrication. Advantageously, the method of manufacture requires only a small number of technological steps to achieve multiple electronic systems S simultaneously, which reduces the time and cost of manufacture.
Ce procédé permet une grande flexibilité de conception. Par ailleurs, la topologie peut être optimisée pour améliorer les performances électriques et thermiques et pour répondre aux besoins d'applications ayant un grand nombre d'entrées/sorties et/ou intégrant des capteurs. L'intégration tridimensionnelle, par utilisation d'une même couche de métallisation ou en intégrant plusieurs couches de métal, permet d'obtenir une miniaturisation optimale sans dégrader les fonctions. Les différents exemples de réalisation ont été décrits pour des composants électroniques se présentant sous la forme de puces électroniques. Néanmoins, il est rappelé que d'autres types de composants électroniques pourraient convenir. This process allows a great flexibility of design. In addition, the topology can be optimized to improve the electrical and thermal performance and to meet the needs of applications with a large number of inputs / outputs and / or incorporating sensors. The three-dimensional integration, using a single layer of metallization or by integrating several layers of metal, provides optimal miniaturization without degrading the functions. The various exemplary embodiments have been described for electronic components in the form of electronic chips. Nevertheless, it is recalled that other types of electronic components may be suitable.

Claims

REVENDICATIONS
1. Procédé de fabrication d'un système électronique (S) comprenant : A method of manufacturing an electronic system (S) comprising:
- une étape d 'application d'un élément sacrificiel (2) sur une pièce de support a step of applying a sacrificial element (2) to a support piece
( 1 ), (1),
- une étape de dépôt d 'au moins un composant électronique (3) sur l 'élément sacrificiel (2) de manière adhésive, chaque composant électronique (3) comportant une surface avant (3A) comportant une pluralité de connecteurs (30) et une surface arrière (3B) opposée à la surface avant (3A), la surface arrière (3B) du composant électronique (3) étant positionnée sur l 'élément sacrificiel (2),  a step of depositing at least one electronic component (3) on the sacrificial element (2) adhesively, each electronic component (3) comprising a front surface (3A) comprising a plurality of connectors (30) and a rear surface (3B) opposite to the front surface (3A), the rear surface (3B) of the electronic component (3) being positioned on the sacrificial element (2),
- une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles (5) réalisées par dépôt métallique de manière, d 'une part, à combler des zones découvertes de l 'élément sacrificiel (2) pour former les ports de connexion (50) du système (S) et, d 'autre part, à former une couche de redistribution reliant les connecteurs (30) du composant électronique (3) aux ports de connexion (50) du système (S), au moins un connecteur (30) et au moins un port de connexion (50) étant écartés d'une distance verticale supérieure à 10 μιτι et interconnectés tridimensionnellement,  a step of producing a plurality of three - dimensional interconnections (5) made by metal deposition so as, on the one hand, to fill open areas of the sacrificial element (2) to form the connection ports (50) of the system (S) and, on the other hand, forming a redistribution layer connecting the connectors (30) of the electronic component (3) to the connection ports (50) of the system (S), at least one connector (30). and at least one connection port (50) being spaced apart by a vertical distance greater than 10 μιτι and interconnected three-dimensionally,
- une étape d 'encapsulation, et  a step of encapsulation, and
une étape de séparation du système (S) de l 'élément sacrificiel (2) .  a step of separating the system (S) from the sacrificial element (2).
2. Procédé selon la revendication 1 , dans lequel l'élément sacrificiel (2) se présente sous la forme d'un film adhésif, en particulier, à double face. 2. The method of claim 1, wherein the sacrificial element (2) is in the form of an adhesive film, in particular, double-sided.
3. Procédé selon l 'une des revendications 1 et 2, dans lequel l 'élément sacrificiel (2) est configuré pour perdre ses caractéristiques d 'adhérence à partir d 'une température prédéterminée. 3. Method according to one of claims 1 and 2, wherein the sacrificial element (2) is configured to lose its adhesion characteristics from a predetermined temperature.
4. Procédé selon l'une des revendications 1 à 3, dans lequel l 'élément sacrificiel (2) est configuré pour perdre ses caractéristiques d 'adhérence suite à une illumination. 4. Method according to one of claims 1 to 3, wherein the sacrificial element (2) is configured to lose its adhesion characteristics following illumination.
5. Procédé selon l'une des revendications 1 à 4, comprenant une étape de réalisation d 'une ouverture (60) dans le système (S) de manière à découvrir la face avant (3A) d 'au moins un composant électronique (3) ayant une fonction de capteur. 5. Method according to one of claims 1 to 4, comprising a step of making an opening (60) in the system (S) so as to discover the front face (3A) of at least one electronic component (3). ) having a sensor function.
6. Procédé selon l'une des revendications 1 à 5, comprenant au moins deux étapes de dépôt d 'une couche de passivation (4, 4'). 6. Method according to one of claims 1 to 5, comprising at least two steps of depositing a passivation layer (4, 4 ').
7. Procédé selon l'une des revendications 1 à 6, comprenant au moins deux étapes de réalisation d'une pluralité d'interconnexions tridimensionnelles (5, 5' ). 7. Method according to one of claims 1 to 6, comprising at least two steps of producing a plurality of three-dimensional interconnections (5, 5 ').
8. Procédé selon l'une des revendications 1 à 7, comprenant une étape de formation d 'un composant passif tridimensionnel (X2) lors de l'étape de réalisation d 'une pluralité d'interconnexions tridimensionnelles (5) . 8. Method according to one of claims 1 to 7, comprising a step of forming a three-dimensional passive component (X2) during the step of producing a plurality of three-dimensional interconnections (5).
9. Procédé selon l 'une des revendications 1 à 8, comprenant une étape de dépôt d 'une couche métallique (91 ) sur la surface arrière (3B) d'au moins un composant électronique (3) . 9. Method according to one of claims 1 to 8, comprising a step of depositing a metal layer (91) on the rear surface (3B) of at least one electronic component (3).
10. Procédé selon l 'une des revendications 1 à 9, comprenant une étape de dépôt d 'au moins deux composants électroniques (3) superposés sur l 'élément sacrificiel (2) et une étape de connexion des connecteurs (30) desdits composants électroniques (3) lors de l'étape de réalisation d 'une pluralité d'interconnexions tridimensionnelles (5). 10. Method according to one of claims 1 to 9, comprising a step of depositing at least two electronic components (3) superimposed on the sacrificial element (2) and a step of connecting the connectors (30) of said electronic components. (3) in the step of producing a plurality of three dimensional interconnects (5).
1 1. Procédé selon l'une des revendications 1 à 10, dans lequel au moins un connecteur (30) et au moins un port de connexion (50) sont écartés d 'une distance verticale supérieure à 1 0 μιτι et interconnectés tridimensionnellement. 1 1. Method according to one of claims 1 to 10, wherein at least one connector (30) and at least one connection port (50) are spaced a vertical distance greater than 1 0 μιτι and interconnected three-dimensionally.
12. Procédé selon la revendication 1 1 , dans lequel au moins une interconnexion possède un rapport de forme supérieur à 2.5 : 1 , de préférence supérieure à 5 :1 , de préférence encore supérieure à 1 0 :1 , pour une distance verticale comprise entre 1 0 μιτι et 100 μιτι. The method according to claim 11, wherein at least one interconnection has a shape ratio greater than 2.5: 1, preferably greater than 5: 1, more preferably greater than 1 0: 1, for a vertical distance between 1 0 μιτι and 100 μιτι.
EP18748941.4A 2017-08-08 2018-08-08 Electronic system and method for the production of an electronic system using a sacrificial member Pending EP3665719A1 (en)

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PCT/EP2018/071513 WO2019030286A1 (en) 2017-08-08 2018-08-08 Electronic system and method for the production of an electronic system using a sacrificial member

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