EP3625884A1 - Convertisseur électrique à couplage galvanique - Google Patents

Convertisseur électrique à couplage galvanique

Info

Publication number
EP3625884A1
EP3625884A1 EP18739750.0A EP18739750A EP3625884A1 EP 3625884 A1 EP3625884 A1 EP 3625884A1 EP 18739750 A EP18739750 A EP 18739750A EP 3625884 A1 EP3625884 A1 EP 3625884A1
Authority
EP
European Patent Office
Prior art keywords
converter
output
semiconductor switch
voltage
inductance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP18739750.0A
Other languages
German (de)
English (en)
Inventor
Marvin TANNHÄUSER
Christopher Fromme
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP3625884A1 publication Critical patent/EP3625884A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck

Definitions

  • the invention relates to a galvanically coupled electrical converter.
  • DC-DC conversion of an input voltage of such as 20 V in an output voltage of, for example 400 V that is galvanically isolated DC-DC converters are used. These usually use an inverter, a transformer and a rectifier with subsequent smoothing to convert the input voltage into the output voltage.
  • the inventive galvanically coupled electrical Wand ⁇ ler for converting an input voltage applied to first terminals in an output voltage comprises an input side connected to the first terminals up converter and an input side with the first connections connected Inverswandler. Furthermore, the converter has a se ⁇ rienscnies of two capacitors connected to the output side positive pole of the boost converter and the output side negative pole of the inverter, the output side negative pole of the boost converter and the output side positive pole of the inverter are connected to each other and to the center terminal between the capacitors ,
  • Such a converter consists of a combination of an up-converter (step-up converter). ler, engl. Boost Converter) with an inverse converter (engl, inverting buck-boost converter) by the series connection of the outputs can provide a comparatively high output voltage ⁇ . Since each of the converter only has to provide half the output voltage, the respective transla ⁇ reduction ratio is significantly reduced compared to the case of a single converter.
  • the transformer is saved and thus achieved an improved efficiency. Since the transformer typically RESIZE ⁇ SSSR and is also more expensive than a simple te inductive compo-, is achieved by the inventive converter also has a smaller size and lower costs for the construction of the wall ⁇ toddlers. Furthermore, it is also possible by the construction of the converter to use both output voltages separately from each other.
  • boost converters and inverters are operated as DC-DC converters.
  • the converter according to the invention can also be operated so that essentially a DC voltage is present at its output in the form of the two capacitors.
  • the nature of the operation is determined by a control device which performs the circuits of the semiconductor switches present in the converters.
  • the control device can also be designed, at the output of the converter a to provide other voltage form than a DC voltage.
  • the boost converter may comprise a first series connection of a first semiconductor switch or a first diode with a second semiconductor switch.
  • the outer terminals of the first series circuit form the output side poles of the boost converter.
  • the boost converter comprises a first inductance, which is connected to the center terminal of the first series circuit and the positive pole of the input voltage.
  • a boost converter is realized.
  • Using a diode enables unidirectional energy flow. If the first series circuit comprises the first semiconductor switch, both directions of energy flow are supported by the up-converter. In other words, to clarify the construction variants, it is repeated that the first series circuit can either have two semiconductor switches or else a semiconductor switch and a diode. Both design variants can be combined with the variants mentioned below.
  • the inverse converter may comprise a second series connection of a third semiconductor switch with a fourth semiconductor switch or a second diode. Of these, one external connection forms the output-side negative pole of the inverter and the other external connection is connected to the positive pole of the input voltage. Furthermore, the inverse converter comprises a second inductance, which is connected to the center terminal of the second series circuit and to the middle terminal between the capacitors.
  • This implements an inverting buck-boost converter.
  • using the second diode enables unidirectional energy flow.
  • the fourth semiconductor switches are supported both energy flow directions from the buck-boost converter.
  • the second series circuit tion can either have two semiconductor switches or a semiconductor switch and a diode. Both construction variants can be combined with the variants mentioned below and above.
  • the converter may have a fifth semiconductor switch between the first inductance and the positive pole of the input voltage. Furthermore, in this case, the converter comprises a sixth semiconductor switch or a third diode between the first inductance and the negative pole of the input voltage.
  • the boost converter may inherently produce only voltages higher than the input voltage clamping ⁇ at its output.
  • the fifth and sixth semiconductor switches it is advantageously possible to represent smaller voltages than the input voltage. If the converter has the sixth semiconductor switch, both directions of energy flow are supported.
  • the transducer comprises the third diode, the energy flow ⁇ direction is supported by the side of the input voltage forth.
  • the converter may include a third inductor serially connected between the first semiconductor switch or the first diode and the second semiconductor switch in the first series connection. This further increases the possible gear ratio for the boost converter.
  • the first and third inductors are constructed as a common inductance with a center tap for the second semiconductor switch. With common inductance is meant that the inductors have a common magnetic circuit, that are arranged on a common core.
  • the converter may comprise a fourth inductor serially connected between the third semiconductor switch and the fourth semiconductor switch or the second diode in the second series circuit.
  • the second and fourth inductance are constructed as a common inductance with a center tap for the third semiconductor switch.
  • common inductance is meant here as in the first and third inductance that the inductors have a magnetic circuit the Common ⁇ men, are thus arranged on a common core.
  • the semiconductor switches of the up-converter and the inverse converter can be operated by the control device in staggered clocking. This has the effect that the switching frequency in the converter appears to be doubled compared to the switching frequency of the semiconductor switches, for example in the boost converter.
  • Inductors and capacitances of EMC filters are thereby reduced.
  • the components are thus significantly smaller and lighter. Since size and weight of these devices typically egg weight ⁇ NEN significant proportion of the overall size and the Truge- have a converter, thereby the entire wall ⁇ ler smaller in appreciably and lighter.
  • the up-converter and the inverse converter can be operated so that their output voltages are the same. Alternatively, they can be operated so that their output voltages are different from each other.
  • the power converter comprises an electrical converter according to the invention. Furthermore, the power converter comprises a full bridge connected in parallel with the series connection of two capacitors with the external terminals, whose center terminals in turn form output terminals for the power converter.
  • the inventive electrical converter is supplemented by the output side connected full bridge to a power converter.
  • the power converter for example, supports an energy flow from the side of the first terminals of the converter to the output terminals of the power converter, in which case the power converter operates as an inverter.
  • the control device of the electrical converter is also responsible for controlling the full bridge for further write-Be ⁇ .
  • the boost converter It is designed for operation as an inverter, to operate the boost converter so that at its output, ie at a first of the capacitors, a first half-wave voltage is generated. Furthermore, the inverse converter is operated so that at its output, so the second of the capacitors, a second half-wave voltage is generated whose polarity is opposite to that of the first voltage.
  • the phase of the half-waves is preferably identical. The polarities of the half-waves then add their amplitudes.
  • half-waves are not perfect. Due to the switching behavior of the respective semiconductor switches, which are switched at high frequencies, the half-wave form has harmonics. Furthermore, the voltage in the boost converter is limited to voltages above the input voltage, so that the half-waveform can not reach the voltage of 0V. So the half-wave needs to be understood, which can only be reached approximately in the Reali ⁇ ty of the electrical converter as idealized th and desired shape.
  • the control device is further configured to control the semiconductor switch of the full bridge so that the applied half-waves are indexed, wherein the polarity of the handoff is switched after each half-wave.
  • the semiconductor switches of the full bridge only have to be switched over at twice the frequency of the half-waves, ie up to a factor of 2 with the frequency corresponding to the alternating voltage generated.
  • the frequency of the generated AC voltage is freely selectable. If an alternating voltage with, for example, mains frequency of 50 Hz is to be generated , the half-waves must be generated at this frequency and the semiconductor switches of the full bridge must be switched at each zero crossing of the AC voltage, ie at 100 Hz.
  • the switching frequency of the semiconductor switches of the full bridge is therefore very low for typical inverter conditions.
  • the described inverter can be used advantageously in ⁇ example, as a solar inverter or battery chargers.
  • the first Se ⁇ rien circuit includes the first diode and the second semiconductor switch and the second series circuit comprises the second diode and the third semiconductor switch, while the first and fourth semiconductor switches are not present.
  • the first and second diodes but the first and fourth semiconductor switches, also in the direction of energy flow from the side of the first terminals of the converter to the output terminals of the power converter. This is the case, for example, in the case of the described generation of half-waves, since energy must be actively removed from the first or second capacitor during the falling edges of the half-waves.
  • the power converter also supports a flow of energy in the reverse direction, in which case expediently the first and fourth semiconductor switches are present, that is to say the first and second series circuits each comprise two semiconductor switches.
  • the power converter works as a rectifier.
  • the power converter may additionally have the following features:
  • the control device is preferably designed to check whether the height of the voltage to be generated by the boost converter is lower than the input voltage.
  • the up-converter can not represent the voltage in this case. This case can occur when the boost converter is to generate a DC voltage at the first capacitor whose level is lower than that of the input voltage. The case may continue to occur when the boost converter generates the halfwaves already described. In this case, there is always a part of the half-wave in which the voltage is lower than the input voltage. Depending on the amplitude of the half-wave, this may even be the case for the entire half-wave.
  • the controller may be configured to take one of two actions.
  • a first measure results from the fact that the up-converter comprises the fifth and sixth semiconductor switches.
  • Control device then controls these two semiconductor switches in addition to generate a voltage below the input voltage. For this it is possible to use two different operating forms
  • either the first and second semiconductor switch for generating the shape of the output voltage can be used during the fifth semiconductor switch switches turned ⁇ and the sixth semiconductor switch is turned off or reversed, the fifth and sixth semiconductor switch for generating the shape of the output voltage used while the first semiconductor switch is turned on and the second semiconductor switch is turned off.
  • the first and second semiconductor switches are used when the output voltage is higher than the input voltage.
  • the fifth and sixth semiconductor switches are used when the Output voltage is lower than the input voltage.
  • the boost converter formed with the first and second semiconductor switches and the buck converter formed with the fifth and sixth semiconductor switches are used alternately in time and independently of each other.
  • a second mode of operation results from the fact that the first, second, fifth and sixth semiconductor switches are switched diagonally. For switching between two switching states, wherein in the first switching state of the first and sixth semiconductor switches are turned on and in the second Wegzu ⁇ state of the second and fifth semiconductor switches are turned on.
  • the boost converter and the buck converter thus operate at the same time and not independently of each other.
  • This second mode of operation has an advantageously simplified control result.
  • a second, alternative measure may be taken by the controller when the boost converter does not include the fifth and sixth semiconductor switches.
  • the full bridge semiconductor switches are used to correct the output voltage of the boost converter.
  • the semiconductor switches of the full bridge are preferably high-frequency, for example with a
  • the power converter can have a third and fourth inductor in series with the output terminals and a capacitor connected between the output terminals. This creates an output filter.
  • the power converter using the fifth and be constructed sixth semiconductor switch. This makes it possible in the boost converter to output lower voltages than the input voltage.
  • Another output terminal of the power converter can be formed by the center connection between the capacitors. This enables operation with a single-phase three-wire network, such as in the USA.
  • the control device can be configured to operate the inverter and the boost converter so that the amplitude of the generated half-wave from the invert converter is different from the amplitude of the half-wave generated by the invert converter. This can advantageously the same
  • Figures 1 to 4 embodiments for the electrical converter Figure 5 is a construction diagram of a photovoltaic system with
  • FIG. 6 shows an embodiment for an inverter using the electrical converter
  • FIGS. 8 to 10 further embodiments for the inverter
  • the transducer 10 corresponds to the structure of an interconnection of an up converter and a home verswandlers, wherein the respective outputs are maral ⁇ tet in series.
  • the converter 10 has a first and second input input terminal IIA, IIB for the input voltage, with the first input terminal IIA to be used as a positive terminal.
  • the transducer 10 has a first and second output terminals 13A, 13B, the first output terminal 13A also typically the positive pole is ⁇ represents.
  • the transducer 10 further includes three electrical bone ⁇ tenivity 12A, 12B, 12C on the basis of which the structure ⁇ be written is.
  • the first node 12A is connected directly to the second input terminal A ⁇ IIB and further connected to ground. Between the first input terminal IIA and the second node 12B, a first inductance LI is angeord ⁇ net. Between the first output terminal 13A and the two ⁇ th node 12B, a first diode Dl is arranged. The first diode Dl is oriented so that a power line from the second node 12 B is made possible. Between the second node 12B and the first node 12A, a second semiconductor switch S2 is arranged.
  • a first capacitor Cl which represents the output of the up-converter, which is formed from the Ers ⁇ th diode Dl, the second semiconductor switch S2 and the first inductance LI.
  • a third semiconductor switch S3 is arranged between the first input terminal IIA and the third node 12C.
  • a second diode D2 is arranged between the second output terminal 13B and the third node 12C.
  • the second diode D2 is oriented so that a power line is enabled from the second output terminal 13B.
  • Zvi ⁇ rule the third node 12C and the first node 12A is disposed a second inductor L2.
  • a second capacitor C2 is arranged, which represents the output of the inverter, that of the second Diode D2, the third semiconductor switch S3 and the second inductance L2 is formed.
  • the semiconductor switches S2, S3 in the converter 10 are in this example GaN switches. However, other switches such as MOSFETs or IGBTs can be used.
  • the boost converter During operation of the circuit, the boost converter generates a positive voltage on the first capacitor Cl. This positive voltage is inherently at least as large as the A ⁇ input voltage at the input terminals IIA, IIB.
  • the inverter in turn, generates a negative voltage at the second output terminal 13B relative to the first node 12A.
  • the output voltage between the two output terminals 13A, 13B is the sum of the amounts of the two voltages generated in magnitude.
  • the gear ratio that results for a given input and output voltage is halved for the boost converter and the inverter converter, respectively.
  • FIG. 2 shows a converter 20 with an alternative construction to the converter 10 of FIG. 1.
  • the structure of the converter 20 differs from the converter 10 according to FIG. 1 in that a first semiconductor switch S1 is now present at the location of the first diode D1.
  • a fourth semiconductor switch S4 is present instead.
  • the operation of the converter 20 can be carried out analogously to the converter 10 according to FIG.
  • the converter 20 can also be extended, in which the target voltages at the capacitors C 1, C 2 are no longer DC voltages, but other waveforms, that is, generally mixed voltages.
  • a Steuerungsein ⁇ direction not shown in the figures provided which is designed for the extended operation to switch the first through fourth semiconductor switch S1 ... S4 so by means of a pulse-width modulation that the desired voltage curve across the capacitors Cl, C2 results.
  • Such a desired voltage curve may, for example, consist of a sequence of half-waves or of a DC voltage with an additional modulation. Furthermore, since the generated voltages at the first and second capacitors C 1, C 2 add to the output voltage, a high amplitude at a moderate transmission ratio for the converter can be achieved even with a mixed voltage.
  • the sequence of half-waves for example, both the up-converter and the inverse converter can produce a phase and amplitude-identical half-wave profile. Then, the amplitudes of the half-waves in the output voltage add to the output terminals 13A, 13B.
  • a limitation in the operation of converter 20 of Figure 2 is that the boost converter can not produce an output voltage below the input voltage. As a result, not all DC voltages and not all mixed voltage characteristics can be generated.
  • a possible solution for this ent ⁇ holds the converter 30 of Figure 3, which represents a further embodiment of the invention.
  • the converter 30 comprises the components of the converter 20 according to FIG. 2.
  • a fourth node 12D is present between the first inductance LI and the first input terminal IIA.
  • a fifth semiconductor switch S5 is arranged between the fourth node 12D and the first input terminal IIA.
  • a sixth semiconductor switch S6 is disposed between the fourth node 12D and the first node 12A.
  • a com bination of ⁇ down and up converter (English, a buck boost converter) is realized.
  • the characteristics of the boost converter can be established. Is an output voltage to be generated, which is lower than the input voltage, the first semiconductor switch is turned on Sl and the second semiconductor switch S2 are turned off, and thus only the down converter ⁇ be used.
  • the restriction of the converter 20 of FIG. 2 with respect to the output voltage is eliminated, and any positive DC voltages and waveforms whose amplitude is not too large can be generated.
  • the first, second, fifth and sixth semiconductor switches S1, S2, S5, S6 can be switched diagonally.
  • the boost converter and the buck converter thus operate at the same time and not independently of each other.
  • the converter 40 according to FIG. 4 is structurally based on the converter 20 according to FIG. In addition to this, however, the converter 40 has a third inductance L3 between the second node point 12B and the first semiconductor switch S1.
  • the first and the third inductance LI, L3 are in this case ⁇ play as a common inductance with center tap ⁇ builds, followed by the second semiconductor switch S2 connects.
  • the converter 40 has a fourth inductance L4 between the third node 12C and the fourth semiconductor switch S4.
  • the second and the fourth inductance L2, L4 are constructed analogously to the first and third inductors LI, L3 in this example as common inductance with center tap, to which the third semiconductor switch S3 is connected.
  • an inverter is constructed with the respective converter 20, 30, 40, which can be used for example as a micro-solar inverter (engl, solar micro-inverter or microinverter).
  • a micro-solar inverter engaging, solar micro-inverter or microinverter.
  • the use of such a micro-solar inverter is roughly sketched in FIG.
  • the inverter 60, 80, 90, 100 is connected to a photovoltaic solar module 51 and to the utility network 52.
  • an inverter 60, 80, 90, 100 is connected in the manner of a micro-solar inverter with exactly one solar module 51 and differs therewith from the conventional string inverter or central inverter.
  • the inverter 60, 80, 90, 100 takes over the conversion of the DC voltage coming from the solar module 51 into a voltage corresponding to the supply network with suitable amplitude, frequency and phase position.
  • FIG. 6 An exemplary structure for a first inverter 60 is shown in FIG. 6.
  • the inverter On the input side, the inverter has a converter 20, which is constructed in accordance with FIG.
  • the output terminals 13A, 13B of the converter 20 do not act as outputs for the inverter 60, but are connected to the external terminals of a full bridge V.
  • the full bridge V comprises four further semiconductor switches S7, S8, S9, S10.
  • the middle terminal of a first half bridge of the full bridge V with the seventh and ninth semiconductor switches S7, S9 is connected to a fifth inductance L5.
  • the middle connection of the second half bridge of the full bridge V with the eighth and tenth semiconductor switch S8, S10 is connected to a sixth inductance L6.
  • the center connections are also connected via a third capacitor.
  • the two center connections are further connected to an EMI filter 61.
  • the output of the EMI filter 61 represents the two output terminals 53A, 53B for the inverter 60.
  • the control device for the inverter 60 which performs the control of the semiconductor switches S1 ... S10.
  • the first and second semiconductor switches S1, S2, ie the up-converter are driven with pulse width modulation in such a way that at the output of the up-converter, ie at the first capacitor C1, the profile of the voltage UC1 takes the form of successive half-waves , This voltage curve is sketched in FIG. 7.
  • the third and fourth semiconductor switches S3, S4, ie the inverse converter are so controlled that at the output of the inverse converter, ie at the second capacitor C2, the course of the voltage UC2 also takes the form of successive half-waves.
  • the up-converter and the inverse converter are thus operated in contrast to the typical operation as a DC-DC converter now so that they produce at their output in each case just no constant DC voltage.
  • the polarity of the voltage UC2 at the second capacitor is such that an increased amplitude of the voltage waveform Zvi ⁇ rule results in sum the first and second output terminals 13A, 13B. With the same amplitude of the two voltage curves UC1, UC2, twice the amplitude for the half-wave results in total.
  • the resulting half-wave is applied to the outer terminals of the full bridge V.
  • the full bridge V is now so ⁇ controlled that the polarity of the half-wave changes with each half-wave and thus results in an ideal sinusoidal voltage waveform between the center terminals of the full bridge V. This is done by switching between two switching states. In the first switching state of the eighth and ninth semiconductor ⁇ switches S8, S9 are switched on, and the seventh and tenth half ⁇ conductor switches S7, S10 off. In the second switching state, the seventh and tenth semiconductor switch S7 is turned on ⁇ S10 and the eighth and ninth semiconductor switch S8, S9 off. The change between these switching states takes place with each half-wave.
  • the control-device is expedient designed to handle this prob ⁇ lem.
  • the control device can be designed, at least in the said time ranges to generate the voltage waveform of the sine wave by the circuit of the semi-conductor switch S7 ⁇ ... S10 of the full bridge V.
  • the semiconductor switches S7 ... S10 must be switched to high-frequency in these time ranges and the voltage form must be set by pulse width modulation.
  • the fifth and sixth inductors L5, L6 and the third capacitor C3 are designed for the necessary filtering of the resulting voltage form even in the case of a high-frequency circuit of the full-bridge V.
  • FIG. 8 shows, as a further exemplary embodiment, an inverter 80.
  • the inverter 80 is constructed approximately like the inverter 60 according to FIG. 6.
  • the inverter 80 according to FIG. 8 is based on the converter 30 according to FIG In other words, in the inverter 80 according to FIG , n
  • the fifth and sixth semiconductor switches S5, S6 are present.
  • the fifth and sixth inductor L5, L6, and the third capacitor C3 is not EXISTING ⁇ .
  • the boost converter is expanded by the fifth and sixth semiconductor switches S5, S6 to a combined up and down converter.
  • the restriction of the output voltage at the first capacitor Cl to voltages above the input voltage thereby eliminated.
  • the control device is configured to use the fifth and sixth semiconductor switches S5, S6 in addition to the first and second semiconductor switches S1, S2 in such a way that the half-wave to be generated is now completely present at the first capacitor C1.
  • the voltages applied to the first and second capacitors C1, C2 thus correspond as completely as possible to the voltage curves UC1, UC2 shown in FIG.
  • the full bridge V will now be described already for the inverter 60 of Figure 6 is controlled such that the half-wave Pola ⁇ rity changes with each half-wave and thus results ⁇ with a sinusoidal ideally voltage waveform across the center terminals of the full bridge V.
  • the eighth and ninth semiconductor switches S8, S9 are switched on and the seventh and tenth semiconductor switches S7, S10 are switched off.
  • the second switching state of the seventh and tenth semiconductor ⁇ switches S7, S10 are turned on and the eighth and ninth half ⁇ conductor switches S8, S9 off.
  • the semiconductor switches S7... S10 can basically switch at the frequency of, for example, 100 Hz. Therefore, even more so than in the case of Inverter 60 that in the full bridge advantageous such switches can be used, which are optimized for low line ⁇ losses.
  • the need for filtering the high-frequency switching is eliminated, whereby the fifth and sixth inductor L5, L6 and the third condensate ⁇ sator C3 become unnecessary.
  • Figure 9 shows as a further embodiment a change ⁇ rectifiers 90, which is designed for use in a single-phase three ladder network (English, split-phase grid).
  • the design of the inverter 90 including the configuration of the control device, largely corresponds to the design of the inverter 60 according to FIG. 6.
  • the first node 12A is provided as a further input for the EMI filter 61 and is led out of it as a neutral conductor.
  • the other functionality corresponds to the change ⁇ judge 60 of Figure 6.
  • FIG. 10 shows, as a further exemplary embodiment, an inverter 100 which is likewise designed for use in a single-phase three-wire network.
  • the construction of the inverter 100 corresponds including Ge ⁇ staltung the controller largely to the structure of the inverter 80 shown in Figure 8, thus has the fifth and sixth semiconductor switches S5, S6 instead of the fifth and sixth inductor L5, L6 and the third capacitor C3 ,
  • the first node 12A is provided as a further input for the EMI filter 61 and is led out of it as a neutral conductor.
  • the other functionality corresponds to the inverter 80 according to FIG. 8.
  • inverter is based on the structure of Figure 4. This construction with inductances with center tap can also be combined with the design variants according to FIGS. 6, 8, 9 and 10.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un convertisseur électrique à couplage galvanique destiné à convertir une tension d'entrée appliquée à des premières bornes en une tension de sortie et comprenant un convertisseur élévateur connecté du côté entrée aux premières bornes, un convertisseur inverseur connecté du côté entrée aux premières bornes et un circuit série, pourvu de deux condensateurs, qui est relié au pôle positif côté sortie du convertisseur élévateur et au pôle négatif côté sortie du convertisseur inverseur. Le pôle négatif côté sortie du convertisseur élévateur et le pôle positif côté sortie du convertisseur inverseur sont reliés à la borne médiane entre les condensateurs.
EP18739750.0A 2017-07-20 2018-06-26 Convertisseur électrique à couplage galvanique Ceased EP3625884A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102017212462.8A DE102017212462A1 (de) 2017-07-20 2017-07-20 Galvanisch gekoppelter elektrischer Wandler
PCT/EP2018/067032 WO2019015920A1 (fr) 2017-07-20 2018-06-26 Convertisseur électrique à couplage galvanique

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EP3625884A1 true EP3625884A1 (fr) 2020-03-25

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EP18739750.0A Ceased EP3625884A1 (fr) 2017-07-20 2018-06-26 Convertisseur électrique à couplage galvanique

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US (1) US11569746B2 (fr)
EP (1) EP3625884A1 (fr)
CN (1) CN110945770A (fr)
DE (1) DE102017212462A1 (fr)
WO (1) WO2019015920A1 (fr)

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Also Published As

Publication number Publication date
CN110945770A (zh) 2020-03-31
DE102017212462A1 (de) 2019-01-24
US20200169171A1 (en) 2020-05-28
WO2019015920A1 (fr) 2019-01-24
US11569746B2 (en) 2023-01-31

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