EP3622786A1 - Élément de compensation de tolérances pour schémas de connexions - Google Patents

Élément de compensation de tolérances pour schémas de connexions

Info

Publication number
EP3622786A1
EP3622786A1 EP18734092.2A EP18734092A EP3622786A1 EP 3622786 A1 EP3622786 A1 EP 3622786A1 EP 18734092 A EP18734092 A EP 18734092A EP 3622786 A1 EP3622786 A1 EP 3622786A1
Authority
EP
European Patent Office
Prior art keywords
compensation element
tolerance compensation
gap
circuit board
pcb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18734092.2A
Other languages
German (de)
English (en)
Inventor
Rüdiger Knofe
Bernd Müller
Jörg Strogies
Klaus Wilke
Rene Blank
Martin Franke
Peter Frühauf
Stefan Nerreter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP3622786A1 publication Critical patent/EP3622786A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y80/00—Products made by additive manufacturing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0425—Solder powder or solder coated metal powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00—Casings, cabinets or drawers for electric apparatus
    • H05K5/0026—Casings, cabinets or drawers for electric apparatus provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units
    • H05K5/0069—Casings, cabinets or drawers for electric apparatus provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units having connector relating features for connecting the connector pins with the PCB or for mounting the connector body with the housing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P10/00—Technologies related to metal processing
    • Y02P10/25—Process efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Tolerance compensation element for circuit diagrams The invention relates to a tolerance compensation element for
  • the heights are not always beinlbar, so that there is the technical problem that very different heights, ie differences> 100 pm, must be compensated in order to ensure a secure contact.
  • the resulting MACHINES SHOW ⁇ chen circuit dimensions are not reli ⁇ permeable to close by the equalization power of Sin ⁇ ter- or conventional soft solder joints.
  • a suitably dimensioned solder application would lead to a lateral outflow of solder in the case of a small-sized gap, as a result of which the high-voltage insulation properties would be significantly worsened. Accordingly, would at a considerably greater dimen ⁇ -dimensioned gap Lot missing, so that the thermal and electrical conductivities possibly also would be adversely affected.
  • the object of the present invention is to provide a tolerance compensation element for circuit diagrams, in particular electronic, as well as a circuit diagram, which can be manufactured individually in a simple manner.
  • this object is achieved by a tolerance equalization element for circuit diagrams, in particular electronic, with a DCB (Direct Copper Bonded) substrate and a PCB (Printed Circuit Board) printed circuit board.
  • the invention is characterized in that a tolerance compensation ⁇ element between DCB substrate and PCB circuit board in a Gap A is set specifically for the contacting of components on the DCB substrate by additive manufacturing and is formed gap-closing.
  • a gap A Zvi ⁇ rule of the PCB board and the DCB substrate producible - ungsrea the PCB - printed circuit board first made ⁇ undersized forth so that a defined distance between DCB substrate (direct copper bonding), and PCB (Printed Circuit board) - printed circuit board is present.
  • the core of the invention is that this distance in the gap A by means of a tolerance compensation element insbesonde re ⁇ a AM-Layer, an additive manufacturing - procedural ⁇ REN is set in a defined and closed.
  • the tolerance compensation element so the AM layer, either on the PCB circuit board or the DCB substrate, preferably in powder form is applied and in particular selectively fused via a laser beam. It is advantageous if the tolerance compensation element is made of a wettable material for conventional solder materials or of an alloy, so that this tolerance compensation element can be connected in the following soldering ⁇ material.
  • the distance between the DCB substrate and the PCB circuit board can be determined directly in the implemented manufacturing process and adjusted to a particular workpiece-specific pairing of the DCB substrate and the PCB circuit board via a closed control loop.
  • a continuation of the inventive concept can consist in that the DCB substrate has a copper-aluminum-copper arrangement (dielectric).
  • Kon ⁇ zepts can consist in that the DCB substrate, a copper - An assembly - Ceramics - copper.
  • An advantageous embodiment of the inventive ⁇ cepts may consist in that the tolerance compensation element is applied in gap A either on the PCB circuit board or the DCB substrate and is selectively fused.
  • a continuation of the inventive concept may consist in that the tolerance compensation element by means of laser ⁇ beam in the gap A is to merge.
  • con ⁇ zepts may be that an electrically PLEASE CONTACT rendes component is a semiconductor component.
  • An advantageous embodiment of the inventive ⁇ cepts may consist in that the gap A between PCB PCB and DCB substrate is made in the manufacturing process of the PCB circuit board with undersize, so that a ge ⁇ targeted distance between DCB substrate and PCB circuit board is trained.
  • a continuation of the inventive concept may consist in that the gaps for the electrical contacting of the semiconductor element are latestbil ⁇ det both for a gap B on the upper side ⁇ as well as in a gap C on the underside of the semicon ⁇ fererbauelements in a narrow tolerance range.
  • a special embodiment of this inventive ⁇ cepts may consist in that the tolerance compensation element is formed of a wettable material for solder materials or of an alloy.
  • An advantageous embodiment of the inventive ⁇ cepts may consist in that the distance in the gap A is to be determined directly in the manufacturing process and is set via a closed loop material specific to the respective pair of DCB substrate and PCB circuit board.
  • the tolerance compensation element according to the invention is arranged between a DCB (direct copper bonded) substrate and a PCB (Printed Circuit Board) printed circuit board
  • the PCB printed circuit board forms a cavity above the DCB substrate into which a component, in particular a semiconductor component, is inserted .
  • ment can be positioned in the event that the elec tronic ⁇ device is a semiconductor device, the DCB substrate has three layers in the composition copper -
  • Ceramic - copper formed Other devices are also conceivable which accept a dielectric as a DCB substrate with a composition copper-aluminum-copper.
  • the semiconductor device has an upper surface which ei ⁇ NEN gap forms B to said PCB board.
  • the semiconductor component has an underside which is positioned over a gap C to the DCB substrate.
  • the gap dimensions for a reliable contact of the electrical component in particular the Halbleiterele ⁇ ments, both on the top side (gap B) and on the lower side ⁇ (gap C)
  • the gap is A between the PCB Lieterplatte and the DCB substrate in the manufacturing process of the PCB - Électte ⁇ te first made with undersize, so that a defined distance between DCB substrate (Direct Copper Bond) and PCB (Printed Circuit Board) - printed circuit board is present.
  • DCB substrate Direct Copper Bond
  • PCB Printed Circuit Board
  • FIG. 1 shows a schematic representation of a circuit arrangement with a tolerance compensation element according to the invention.
  • the PCB - Fig. 1 shows a switching arrangement with an inventive tolerance compensation element which rect between a DCB ((di- Bonded Copper).
  • Printed circuit board 2 forms a cavity 4 above the DCB substrate 1, into which an electronic component 5, in particular a semiconductor component 6, are positioned can.
  • the DCB substrate 1 is layered three ⁇ , preferably in the composition copper - copper formed - Kera ⁇ mik.
  • Other devices 5 are also conceivable which accept a dielectric as DCB substrate 1 with a composition copper-aluminum-copper.
  • the semiconductor device 6 has an upper side 7, which forms a gap B 8 to the PCB circuit board 2.
  • the semiconductor component 6 has an underside 9, which is positioned over a gap C 10 to the DCB substrate 1.
  • the gap A 3 between the PCB Porter ⁇ plate 2 and the DCB substrate 1 in the manufacturing process of the PCB - 2 is initially made with undersize, so that a defined Distance between DCB substrate (Direct
  • the tolerance compensation element in particular ei ⁇ ner AM layer, defined by an additive manufacturing - method set and closed.
  • the tolerance compensation element that is to say the AM layers, is either applied to the PCB circuit board 2 or the DCB substrate 1, preferably in powder form, and in particular selectively fused by means of a laser beam.
  • the tolerance compensation element according to the invention for electronic circuit diagrams is characterized by the fact that it can be processed in a simple , individual manner in an additive manufacturing Process for gap closure between a DCB substrate and a PCB circuit board can be designed and manufactured.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un élément de compensation de tolérances destiné à des schémas de connexions comprenant un substrat DCB (Direct Copper Bonded) (1) et une carte de circuit imprimé PCB (Printed Circuit Board) (2) et un schéma de connexions pourvu de cet élément de compensation de tolérance. L'invention est caractérisé en ce qu'un élément de compensation de tolérance est inséré de manière ciblée entre le substrat DCB (1) et la carte de circuit imprimé PCB (2) dans un intervalle A (3) pour la mise en contact de composants (5) sur le substrat DCB (1) par fabrication additive et est conçu pour fermer l'intervalle.
EP18734092.2A 2017-07-04 2018-06-07 Élément de compensation de tolérances pour schémas de connexions Pending EP3622786A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102017211330.8A DE102017211330A1 (de) 2017-07-04 2017-07-04 Toleranzausgleichselement für Schaltbilder
PCT/EP2018/064983 WO2019007624A1 (fr) 2017-07-04 2018-06-07 Élément de compensation de tolérances pour schémas de connexions

Publications (1)

Publication Number Publication Date
EP3622786A1 true EP3622786A1 (fr) 2020-03-18

Family

ID=62748911

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18734092.2A Pending EP3622786A1 (fr) 2017-07-04 2018-06-07 Élément de compensation de tolérances pour schémas de connexions

Country Status (5)

Country Link
US (2) US20200122450A1 (fr)
EP (1) EP3622786A1 (fr)
CN (1) CN110870391A (fr)
DE (1) DE102017211330A1 (fr)
WO (1) WO2019007624A1 (fr)

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Publication number Priority date Publication date Assignee Title
CN110421839B (zh) * 2019-07-26 2021-09-28 成都职业技术学院 基于3d打印的二极管及其打印方法

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Also Published As

Publication number Publication date
US20200122450A1 (en) 2020-04-23
CN110870391A (zh) 2020-03-06
WO2019007624A1 (fr) 2019-01-10
DE102017211330A1 (de) 2019-01-10
US20230189450A1 (en) 2023-06-15

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