Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
  • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
  • H01L25/117—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
  • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
  • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49838—Geometry or layout
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5385—Assembly of a plurality of insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
  • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
  • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10007—Types of components
  • H05K2201/10166—Transistor

Definitions

• the invention generally relates to the field of power electronics. More particularly, the invention relates to a method of integration of power electronic chips allowing parallel manufacturing. The invention also relates to electronic devices and power modules obtained by the implementation of the aforementioned method.
• Power electronic circuits such as power modules
• power electronics are very present in many fields of activity such as transport, industries, lighting, heating, etc.
• energy transition towards renewable and less CO2-emitting energy sources power electronics will become more widespread and will have to respond to increasing economic and technological constraints.
• transport sector the automobile industry is subject to very stringent emission standards for polluting discharges that lead to a real technological change with the electrification of vehicles.
• the electrification of vehicles faced with the heavy constraints of weight, bulk and cost that predominate in this mass production industry requires technological advances in the processes of integration of power electronic chips.
• HDI technology "High Density Interconnect” in English
• PCB printed circuit boards
• TLP welding transient liquid phase welding
• sintering of metal nanoparticle powder it is usual to use the so-called HDI technology, "High Density Interconnect” in English, to increase the level of integration and reduce the size of the power modules.
• the HDI technology generally implemented on printed circuit boards known as PCB, from the “Printed Circuit Board” in English, is based on an optimization of the spatial implantation of the components by using, in particular, thinner interconnection tapes and micro-holes. interconnection called “microvias”. It is used laser beam drilling as well as various welding techniques such as for example brazing, transient liquid phase welding known as TLP welding or sintering of metal nanoparticle powder.
• the application DE102014010373A1 proposes an electronic module comprising first and second printed circuit boards which are superimposed and each include an electronic component. A sintering process is used to link the cards together. Furthermore, the application US2016 / 133558A1 describes a power module comprising a central printed circuit board which is sandwiched between two heat dissipation plates. Electronic components are located in the central card.
• HDI technology finds its limits in the face of cost reductions that are necessary for mass production and increasing the level of integration and compactness. Indeed, some techniques used, such as laser drilling, do not facilitate the parallelization of manufacturing processes and hinder cost reductions.
• the level of integration that can be achieved is limited by the volume occupied by the interconnections with ribbons and microvias. These interconnections with ribbons or cables introduce parasitic inductances that oppose higher switching or switching frequencies. The reduction of parasitic inductances is necessary to reduce the heat generated and to protect the circuit against potentially destructive overvoltages. However, the increase in switching frequencies is favorable for compactness, particularly in power converters. [009] Increasing the level of integration and the compactness of the electronic power modules accentuate the thermal stresses on the components. High performance cooling is required to maintain the junction temperatures of the active components below critical values, to achieve thermal equilibrium and to ensure the reliability of the power modules. For this, the architecture of the power modules and the technologies used must allow extraction of the energy dissipated closer to the components.
• the invention relates to a method for integrating power electronic chips for producing a laminated subassembly for an integrated electronic power device.
• the method comprises:
• first and second blanks including a use of space reservation means, each of the blanks being made by laminating insulating and conductive inner layers on a metal base plate, at least one electronic chip being implanted in one or the other of the first and second blanks, and the first and second blanks being made with complementary profiles of their high lamination surfaces;
• the space reservation means are used for the realization of at least one location for said at least one chip.
• the production of the first and second blanks also includes a use of indexing and setting elements for the production of at least one of the inner layers.
• the lamination of the insulating and conductive inner layers of the first and second blanks is carried out on a copper metal base plate.
• the laminating insulating and conducting internal layers are formed with so-called IMS type techniques.
• dielectric portions of prepreg stage B are made from a stage B prepreg sheet by die stamping and / or a cutter with a cutter and / or a blade and are located in respective locations of the blanks.
• conductive portions are made from a copper foil by die stamping and / or a cutter with a milling cutter. and / or at the blade and are implanted in respective locations of the blanks.
• dielectric and conductive portions are made from a copper-coated laminate by die stamping and / or cutting. with the cutter and / or blade or laser, and are located in respective locations of the blanks.
• the formation of the inner layers includes a precise definition of connection patterns by photolithography.
• the formation of the inner layers includes a deposition of a first-level electrical interconnection material at specific locations including locations dedicated to said minus an electronic chip, the deposition being carried out using a solder paste distributor.
• the press assembly of the first and second blanks includes a vacuum lamination bake.
• the invention also relates to an integrated electronic power device in the form of an electronic power module, the device comprising first and second laminated subassemblies produced by the implementation of the method such as briefly described above and a central coolant circulation space arranged between the first and second subassemblies, the first and second laminated subassemblies being superimposed and bonded together and comprising respectively first and second electronic power switches. forming a bridge branch.
• the electronic power switches are transistors of the MOSFET or IGBT type.
• FIGS. and 1b show two transistor bridge branch schemes, with MOSFET transistors and IGBT transistors;
• Figs.2 to 10 are simplified sectional views showing steps of the method of integrating electronic chips according to the invention;
• Figs. 1 and 12 are simplified sectional views showing first and second embodiments of a power module according to the invention, for an air-cooled module and a liquid-cooled module.
• FIG. 1a A particular embodiment of the method according to the invention is now described above in the context of the realization of a power module in the form of a bridge branch, or half bridge, switching to transistors.
• Two examples of power modules are shown in Figs. 1a and 1b. These modules can be associated to form complete switching bridges or associated in parallel to pass the desired current.
• FIG. 1 shows a diagram of a first BM bridge branch formed of MOSFET, MTHS and MTLS transistors, and of MDHS and MDLS diodes respectively associated with the transistors.
• Fig. 1b shows a diagram of a second bridge branch B1 formed of IGBT, ITHS and ITLS transistors, and their associated IDHS and I DLS diodes.
• the power module manufactured is a bridge branch BM as shown in Fig.la, that is to say, comprising two transistors MOSFET, MTHS and MTLS. , and MDHS and MDLS diodes respectively associated with the transistors.
• the diodes associated with the transistors will already be integrated in the chips of the transistors, so that their implantations will not be necessary.
• the manufactured power module and the bridge branch both have a reference reference BM below. It will also be noted that this description also applies to the bridge branch B1 of FIG. 1b, replacing the MOSFET transistors with IGBT transistors.
• Fig.2 shows a blank EB1, at an initial stage, a subset of a power module.
• space reservation elements HM1 and HM2 are firstly placed on high surfaces SH1 and SH2 of a metal base plate MB1, respectively .
• the metal base MB1 is preferably made of copper.
• the metal base MB1 is profiled beforehand so as to form the high surfaces HM1 and HM2 and MP locations.
• the prior profile of the MB1 metal base is typically obtained by mechanical removal of material or photolithography.
• Dielectric portions PPb of prepreg stage B are deposited on the base plate MB1 at respective locations MP thereof.
• the dielectric portions PPb of stage B prepreg are typically here woven glass fiber dielectrics coated with an epoxy type resin and partially polymerized. Other dielectrics such as Teflon (trademark) or polyimide may, however, be used for special applications.
• the dielectric portions PPb may be obtained by die stamping of a stage B prepreg sheet, or by cutting with a cutter or blade. In the step shown in FIG.
• indexing and setting elements LM1 and LM2 are arranged on either side of the space reservation elements HM1 and HM2. These elements LM1, LM2, abut against the conductive portions PPb and their function is to define the place of copper conductive portions CP which partially overlap the dielectric portions PPb. NC portions not covered by the conductive portions CP, marked in Fig.4, are left at the side walls of the locations MP.
• the conductive portions CP are obtained from a copper foil by die stamping or by cutting with a cutter or blade.
• the layering of the portions PPb and CP on the MB1 metal base is obtained by vacuum pressing or vacuum lamination.
• the dielectric portions PPb are shown in FIG. 3 in their polymerized form as a dielectric layer PP.
• the laminated blank EB1 of Fig.3 from a copper coated laminate called CCL ("Copper Clad Laminate" in English).
• CCL Copper Clad Laminate
• the laminate portions formed of a dielectric layer and a copper coating are cut from a laminate panel and reported in the MP locations which may if necessary be pre-coated with resin.
• the stratification of the laminate portions on the MB1 metal base is obtained by vacuum pressing or vacuum lamination.
• the indexing and setting elements LM1 and LM2 have been removed and reveal NC parts not covered by the conductive portions CP.
• Figs.5 and 6 show a photolithography operation for defining with high precision the copper connection patterns.
• a photoresist PS is coated on the high lamination surfaces of the blank EB1.
• the surface portions to etch in wet etching are then defined and released in a conventional manner using a screen printing mask and exposure to ultraviolet radiation.
• the blank EB1 is shown ready for wet etching copper.
• a metal portion CP1a is removed and the connection pattern is thus accurately made.
• the PS photoresist resin was removed by known methods such as, for example, oxygen plasma treatment, dry etching or solvent removal.
• the connection pattern comprises a conductive portion CP2 defined precisely after the etching of the portion CP1.
• the step shown in Fig.7 relates to the shaping of locations L1 and L2 for respectively receiving the chip of a transistor MT and the chip of a diode MD.
• the spaces reserved by the elements HM1 and HM2 are dedicated respectively to the locations L1 and L2.
• dielectric portions PPb1 of prepreg of stage B are deposited in several layers, on surface portions of the blank EB1. This step makes it possible to configure the cavities and the electrical insulation parts necessary for the removal of the electrical interconnection material and the implantation of the electronic chips.
• the dielectric portions PPb1 are obtained and implanted in a similar manner to the portions PPb of FIG.
• the location L1 comprises two cavities L10 and L1 1 for receiving an electrical interconnection material.
• the cavity L10 corresponds to the space reserved by the element HM1 and is provided for the electrical contact between the base plate MB1 and a drain electrode (DHS or DLS in FIG. 1a) of the transistor MT.
• the cavity L11 is formed by the removal of the dielectric portions PPb1 and is provided for the electrical contact between the conductive portion CP2 and a gate electrode (GHS OR GLS in Fig. 1a) of the transistor MT.
• the location L2 comprises a cavity L20 entirely defined by the space reservation element HM2 and intended for the electrical interconnection material.
• the cavity L20 is provided for electrical contact between the base plate MB1 and a cathode electrode (Fig.l a) of the diode MD.
• the space reservation elements HM1 and HM2 are removed and the chips of the components MT and MD are put in place in the locations L1 and L2 after the removal of a material electrical interconnection.
• the dielectric portions PPb1 of prepreg stage B are shown as fully polymerized and forming PP dielectric layers. Note however that this manufacturing step can be performed while the PPb1 portions remain not fully polymerized.
• the electrical interconnection material EU is deposited in cavities L10, L11 and L20.
• the electrical interconnection material EU is typically a solder paste which is adapted to a FLI type interconnection of "First Level Interconnect" in English.
• the deposition of the first level electrical interconnection material EU is carried out using a solder paste distributor.
• Fig.9 shows the assembly of the blank EB1, obtained by the manufacturing steps of Figs.2 to 8, and a complementary blank EB2.
• the blank EB2 is produced by following manufacturing steps similar to those of the blank EB1. It should be noted that drafts EB1 and EB2, in accordance with the invention, are manufactured in parallel on different manufacturing lines, which allows a consequent decrease in manufacturing time.
• the high lamination surface profile of the blank EB2 is complementary and matches that of the blank EB1.
• the blank EB2 has locations L3 and L4 which respectively correspond to the locations L1 and L2 of the blank EB1.
• the surfaces of the locations L1 and L2 are covered with a first level electrical interconnection material EI2, identical to the EU material of the substrate EB1, for the electrical connection of a source electrode (SHS OR SLS in FIG. and an anode electrode (Fig.la) of transistor chips MT and diode MD to a metal base plate BM2 of the blank EB2, respectively.
• SHS OR SLS source electrode
• Fig.la anode electrode
• the blank EB2 comprises dielectric portions PPb2 of prepreg stage B which are arranged in correspondence with the dielectric portions PP (PPb1) of the blank EB1. As shown in Fig.9, the blanks EB1 and EB2 are pressed against each other and trap chips MT and MD components in their inner layers. Final assembly and obtaining of the laminated subassembly is achieved by vacuum pressing or vacuum laminating. The final polymerization of the dielectric portions and the connections with the electrical interconnection material occur during this final assembly.
• Fig.10 shows a variant of the assembly step of Fig.9.
• the first level electrical interconnection material EI2 is deposited on the upper faces of the electronic chips MT and MD in correspondence with the locations L3 and L4 of the blank EB2.
• Final assembly is then performed in the same manner as described above for Fig.9.
• the method according to the invention authorizes the manufacture of power subassemblies or complete power electronic devices with a laminated sandwich architecture.
• the process proposed here allows both a reduction of the time manufacturing process brought about by the parallelization of the chip integration process and the use of proven and economical IMS-type techniques, increased performance and increased compactness.
• the optimization of the internal connectivity of the subassemblies, carried out without vias or microvias, allows in particular a reduction of parasitic inductances and more integration.
• These power modules EM1 and EM2 are built by stacking two laminated subsets BBHS and BBLS manufactured in a similar manner to that described above with reference to Figs.2 to 10.
• the laminated subassemblies according to the invention are elementary bricks that can be assembled to form integrated electronic power devices of greater or lesser complexity.
• the assembly of two stacked elementary bricks is typically carried out in press and in the oven. The mechanical and electrical connections between the two bricks will be ensured by welding.
• the EM1 module shown in Fig. 1 is an air-cooled embodiment.
• a power converter formed by the assembly of several power modules EM1 may be equipped if necessary heat dissipation means. These heat dissipation means will comprise one or more radiators in thermal contact, electrically isolated, with the copper parts MB1, MB2.
• the architecture of the invention allows efficient extraction of calories dissipated with conventional radiators, thus avoiding in a number of applications to use more expensive means such as phase change cooling devices.
• the mechanical and electrical connection at the IP junction plane between the BBLS and BBHS bricks of FIG. 10 can be obtained by a transient liquid phase welding known as TLP, a sintering connection or by other techniques. solder indicated above. As shown in FIG.
• the EM module 1 is equipped here with a control circuit CTRL arranged at the top of the module and electrically isolated by a DLHS dielectric layer, from the copper part MB1 of the BBHS brick.
• a DLLS dielectric layer is arranged at the bottom of the module and provides electrical isolation of this part of the BBLS brick.
• the CTRL circuit comprises several laminated layers made according to the techniques described above. Active and passive components may, if necessary, be buried between the inner layers of the CRTL circuit, or else surface-mounted on the circuit in conventional manner by soldering or conductive glue.
• the EM2 module shown in FIG. 12 is a liquid-cooled embodiment which is suitable for high power applications.
• the module EM2 also comprises a space CC coolant circulation.
• a dielectric liquid for cooling under pressure may for example be used as a coolant coolant.
• the space CC is provided in the central part of the module EM2, in direct contact with the copper plates ⁇ 1 and MB2 bricks BBLS and BBHS, respectively.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Geometry (AREA)
• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)

Applications Claiming Priority (2)

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• 2016
  • 2016-12-12 FR FR1662335A patent/FR3060255B1/fr active Active
• 2017
  • 2017-12-05 WO PCT/FR2017/053392 patent/WO2018109315A1/fr active Application Filing
  • 2017-12-05 EP EP17822726.0A patent/EP3552235A1/fr active Pending
  • 2017-12-05 US US16/468,448 patent/US10734368B2/en active Active
  • 2017-12-05 JP JP2019551752A patent/JP2020501381A/ja active Pending
  • 2017-12-05 CN CN201780086323.9A patent/CN110291633B/zh active Active

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