EP3523825A4 - Dispositif tridimensionnel à semi-conducteur et structure - Google Patents

Dispositif tridimensionnel à semi-conducteur et structure Download PDF

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Publication number
EP3523825A4
EP3523825A4 EP17859869.4A EP17859869A EP3523825A4 EP 3523825 A4 EP3523825 A4 EP 3523825A4 EP 17859869 A EP17859869 A EP 17859869A EP 3523825 A4 EP3523825 A4 EP 3523825A4
Authority
EP
European Patent Office
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP17859869.4A
Other languages
German (de)
English (en)
Other versions
EP3523825A2 (fr
Inventor
Zvi Or-Bach
Jin-Woo Han
Brian Cronquist
Eli Lusky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Monolithic 3D Inc
Original Assignee
Monolithic 3D Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Monolithic 3D Inc filed Critical Monolithic 3D Inc
Publication of EP3523825A2 publication Critical patent/EP3523825A2/fr
Publication of EP3523825A4 publication Critical patent/EP3523825A4/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP17859869.4A 2016-10-10 2017-09-19 Dispositif tridimensionnel à semi-conducteur et structure Pending EP3523825A4 (fr)

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US201662406376P 2016-10-10 2016-10-10
US201662432575P 2016-12-11 2016-12-11
US201662440720P 2016-12-30 2016-12-30
US201762457838P 2017-02-11 2017-02-11
US201762460989P 2017-02-20 2017-02-20
US201762471963P 2017-03-16 2017-03-16
US201762480529P 2017-04-02 2017-04-02
US201762484398P 2017-04-12 2017-04-12
US201762488821P 2017-04-23 2017-04-23
US201762517152P 2017-06-08 2017-06-08
US201762530173P 2017-07-08 2017-07-08
US201762535265P 2017-07-21 2017-07-21
US201762549952P 2017-08-24 2017-08-24
PCT/US2017/052359 WO2018071143A2 (fr) 2016-10-10 2017-09-19 Dispositif tridimensionnel à semi-conducteur et structure

Publications (2)

Publication Number Publication Date
EP3523825A2 EP3523825A2 (fr) 2019-08-14
EP3523825A4 true EP3523825A4 (fr) 2020-09-09

Family

ID=61905833

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17859869.4A Pending EP3523825A4 (fr) 2016-10-10 2017-09-19 Dispositif tridimensionnel à semi-conducteur et structure

Country Status (3)

Country Link
EP (1) EP3523825A4 (fr)
CN (1) CN109952643B (fr)
WO (1) WO2018071143A2 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10839872B2 (en) * 2018-07-03 2020-11-17 Ememory Technology Inc. Random bit cell using an initial state of a latch to generate a random bit
US10847236B2 (en) * 2018-10-17 2020-11-24 Ememory Technology Inc. Memory cell with a sensing control circuit
KR20200053919A (ko) * 2018-11-09 2020-05-19 에스케이하이닉스 주식회사 수직형 메모리 장치 및 그 제조 방법
US10861722B2 (en) * 2018-11-13 2020-12-08 Applied Materials, Inc. Integrated semiconductor processing
US10741535B1 (en) * 2019-02-14 2020-08-11 Sandisk Technologies Llc Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same
CN111430366B (zh) * 2019-02-26 2021-02-09 长江存储科技有限责任公司 三维存储器件及其形成方法
WO2020220280A1 (fr) * 2019-04-30 2020-11-05 Yangtze Memory Technologies Co., Ltd. Dispositif de mémoire tridimensionnel à mémoire vive dynamique intégrée
CN110530969B (zh) * 2019-08-14 2021-05-25 江苏大学 一种基于掺杂金属原子的石墨烯谐振式气体传感器的制备工艺
CN113451269B (zh) * 2020-03-25 2022-07-22 长鑫存储技术有限公司 字线结构和半导体存储器
US11856781B2 (en) * 2020-07-22 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11704271B2 (en) * 2020-08-20 2023-07-18 Alibaba Group Holding Limited Scalable system-in-package architectures
US11232824B1 (en) 2020-12-11 2022-01-25 International Business Machines Corporation Non-volatile analog resistive memory cells implementing ferroelectric select transistors
CN112687522A (zh) * 2020-12-24 2021-04-20 上海集成电路研发中心有限公司 一种非晶锗硅薄膜结构、集成结构以及制造方法
US11545220B2 (en) * 2020-12-29 2023-01-03 Micron Technology, Inc. Split-gate memory cells
EP4024222A1 (fr) 2021-01-04 2022-07-06 Imec VZW Circuit intégré avec partitionnement 3d
CN112768366B (zh) * 2021-01-22 2024-02-23 长江存储科技有限责任公司 半导体结构及其制备方法
KR20220150552A (ko) * 2021-05-04 2022-11-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
CN113782461B (zh) * 2021-08-20 2024-04-09 长江存储科技有限责任公司 半导体结构的测试方法以及测试样品
JP2023041280A (ja) * 2021-09-13 2023-03-24 キオクシア株式会社 記憶装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120182801A1 (en) * 2011-01-19 2012-07-19 Macronix International Co., Ltd. Memory Architecture of 3D NOR Array
US20150340366A1 (en) * 2014-05-21 2015-11-26 Joon-Sung LIM Semiconductor devices including a peripheral circuit region and first and second memory regions, and related programming methods

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7291878B2 (en) * 2003-06-03 2007-11-06 Hitachi Global Storage Technologies Netherlands B.V. Ultra low-cost solid-state memory
DE102007008530B4 (de) * 2007-02-21 2015-11-12 Infineon Technologies Ag Verfahren zum Herstellen einer nichtflüchtigen Speichervorrichtung, nichtflüchtige Speichervorrichtung, Speicherkarte mit einer nichtflüchtigen Speichervorrichtung und elektrisches Gerät mit einer Speicherkarte
US7897431B2 (en) * 2008-02-01 2011-03-01 Promos Technologies, Inc. Stacked semiconductor device and method
US7983065B2 (en) * 2009-04-08 2011-07-19 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
US8754533B2 (en) * 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8581349B1 (en) * 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
EP3460845A1 (fr) * 2010-07-30 2019-03-27 Monolithic 3D Inc. Dispositif et système semi-conducteur 3d
US8724393B2 (en) * 2011-05-02 2014-05-13 Macronix International Co., Ltd. Thermally assisted flash memory with diode strapping
US8574929B1 (en) * 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9691760B2 (en) * 2013-03-12 2017-06-27 Monolithic 3D Inc Semiconductor device and structure
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
US9099538B2 (en) * 2013-09-17 2015-08-04 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3D device
US9568940B2 (en) * 2013-12-05 2017-02-14 International Business Machines Corporation Multiple active vertically aligned cores for three-dimensional chip stack
KR102275540B1 (ko) * 2014-12-18 2021-07-13 삼성전자주식회사 가변 저항 메모리 소자

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120182801A1 (en) * 2011-01-19 2012-07-19 Macronix International Co., Ltd. Memory Architecture of 3D NOR Array
US20150340366A1 (en) * 2014-05-21 2015-11-26 Joon-Sung LIM Semiconductor devices including a peripheral circuit region and first and second memory regions, and related programming methods

Also Published As

Publication number Publication date
CN109952643A (zh) 2019-06-28
WO2018071143A2 (fr) 2018-04-19
CN109952643B (zh) 2024-05-31
WO2018071143A3 (fr) 2018-07-26
EP3523825A2 (fr) 2019-08-14

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